Long delay when am335x and PMIC TPS65217 are powering off

Oleg Strelkov,

It looks like you use the SEQDWN bit.  This will only shutdown the power rails (DCDC's and LDO's/LS's) in ACTIVE mode, meaning the SYS pin will still be high. Are you powering down all your power rails? Have you modified your power down sequence, or are you using the default?  

If you look at the global state diagram, figure 1, you will see moving from ACTIVE state to OFF state there is a 1s delay from when PWR_EN goes low, plus the 1 second delay from your algorithm. That at least accounts for two seconds of what you are seeing.

Do you have to use the alarm2 solution. Could you just set the OFF bit and pull PWR_EN low?

Janice

Hi, Janice,

I use default power down sequence.

I understand that SYS pin will be high.

Yes, I use SEQDWN bit.

I set OFF bit in STATUS register, then set SEQDWN bit in SEQ6 register and then pull down PWR_EN pin.

Channel 2 of screenshot is PWR_EN signal (It pulls down in the center of screen. Dotted vertical cursor marks this moment).

Channel 3 is VLDO2 pin.

Channel 4 is SYS pin (SYS1, SYS2), AC powering.

Rails VLDO2 and others power down after 2.52 sec delay (second dotted cursor).

Why?

What is reason of this delay?

Can I reduce this delay (ideally to switch off immediately)?

Best regards,

Oleg.

Janice,

I forgot discuss global state diagram.
Yes, I see 1s delay from ACTIVE state to OFF state.
In powering off algorithm I use RTC to pull down PWR_EN signal. And I have 1s delay due to RTC.
But this delay is happened before pulling down PWR_EN signal (Please see left side of screenshot. Channel 1 is GPIO button signal. It has high level from powering on. When I press button then software detects low level GPIO input, sets PMIC bits and programs RTC ALARM2 event. You can see about 2 seconds interval between failing GPIO signal and failing PWR_EN signal).

So we have 1s delay from PMIC global state diagram.
But really I watch more long delay about 2.52 sec.
Is it normally?
I would like to reduce it. Is it possible?

Best regards,
Oleg.

Oleg,

In your algo you are doing both set OFF bit + pulling PWR_EN low and setting the SEQDWN bit, do only one as the SEQDWN is just for testing. I would also measure your delay from when PWR_EN goes low to when the first rail of the power down sequence goes low, instead of measuring to SYS pin (I think that is giving you extra delay because it is after all the rails have gone down so it is incorporating all their delays for the power down sequence). Also to help isolate the issue measure without your ALARM2 solution algo, just do a write to pull PWR_EN low. Thanks for your patience.

Janice

 

Hi, Janice,

Thank you for your responce.

Unfortunately I can't provide pull PWR_EN low without ALARM2 solution from Sitara. (please read Biser Gatchev-XID answer:  http://e2e.ti.com/support/arm/sitara_arm/f/791/p/483624/1743545#1743545 )

I followed your recommendation and used in my algo SEQDWN bit only (without OFF bit). On new attached screenshot (seqdwn_only.png):

channel 3 (blue) - PWR_EN,
channel 4 (green) - rail DCDC3 (VDD_CORE).
Delay from PWR_EN low to DCDC3 low is 3.5 sec.

But in this mode PMIC & am3359 is powered off, but after 1 sec is powered on and continuosly restarts with 6 sec period.

So I tried to set OFF bit only (without SEQDWN bit). Results you can see on next screenshot (off_only_1.png)

Channels assignment is the same.
Delay is 3.64 sec on this screenshot.

On the last screenshot (off_only_2.png) I pulled down PWR_EN signal later and we have delay 2.42 sec.

But in both cases 5 seconds is elapsed from power-up moment to power-down moment.
It looks like PMIC is busy after power-up and can't begin powering off procedure before 5 seconds delay.
What does it mean? What is the magic 5s delay? It isn't mentioned in datasheet.

Best regards,
Oleg.