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TPS54618Q1/input timing of an external clock

tsuyoshi tokumoto
Expert 2630 points
Other Parts Discussed in Thread: TPS54618

Hi all,

  My customer is designing a prototype including the TPS54618Q1.
  The switching frequency of TPS54618Q1 is synchronized to an external clock.
  I have a question about the timing of inputting the external clock and an
  Enable signal.
  If the external clock and the Enable signal become active at the same time,
  will there be any problem?
      *Cf. attached file TPS54618Q1_extclk2.xlsx

tps54618q1_extclk2.xlsx

  If there is any problem,could you please tell me the recommended timing?


Best regards.
Tsuyoshi Tokumoto 

  • 0
    TI__Guru**** 191445 points
    There will be some delay between rising edge of EN and the start of switching. It should be ok to have CLK present with EN. Are you using the same signal to enable the TPS54618 and enable the CLK buffer?
  • 0 in reply to JohnTucker
    Expert 2630 points

    Hello Tucker-san,

    Thank you very much for your prompt reply.

    Please let me ask additional question.

    I think that when the EN pin is Low level,most of the internal
    bias circuit in TPS54618Q1 doesn't work.

    When the low impedance high level signal is applied to the RT pin
    under the conditions that the internal bias circuit does not work,
    does some of the internal circuit not have unexpected behavior?


    My customer will control the Enable signal and the external clock
    signal by MCU,and the external clock and the Enable signal become
    active at almost the same time currently.

    Best regards.
    Tsuyoshi Tokumoto