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TPS7A4701 Powering Up Into A Load

Daniel Jackson
Intellectual 575 points
Other Parts Discussed in Thread: TPS7A47

In a TPS7A4701 design underway here, the LDO will have +5V applied as input, but with the EN input initially false. Prior to EN being asserted true, approximately +1V will unavoidably be applied to the output. Is the LDO expected to be able to turn on (via EN being asserted) into such a load without problem?

  • 0
    TI__Guru 55940 points
    Hi Daniel,

    TPS7A47 does have the capability to startup from a prebiased state. Please note that the LDO will not regulate until it reaches its programmed output voltage. Also it is important to consider the possibility of reverse current when looking at sequencing. If I am understanding correctly, 5V will be present at Vin when Vout is biased to 1V. Under this condition, there would be no reverse current concerns as Vin is greater than Vout.

    Very Respectfully,
    Ryan
  • 0 in reply to Ryan Eslinger
    Intellectual 575 points
    Ryan,

    Thanks for your response.

    The only reverse current situation that should occur may be at power down. The datasheet however does not mention needing to protect the IC from normal powerdown situations, where output voltage exists as a result of the LDO producing same, but then the input source is shutoff (EN may or may not have been deasserted). Is some sort of diode (or other) protection required for the LDO? If so, why is this not mentioned in the datasheet?
  • 0 in reply to Daniel Jackson
    TI__Guru 55940 points
    Hi Daniel,

    LDOs are not designed to sink current. Reverse current applications are fairly rare and can usually be avoided through sequencing the rails. If reverse current conditions are expected, a robust design will include external protection.

    Very Respectfully,
    Ryan
  • 0 in reply to Ryan Eslinger
    Intellectual 575 points

    The application here is straightforward, with a reverse current situation not a problem or consideration, except for the usual situation of when the LDO is commanded to turn off (via EN) or the input power is removed, some charge will continue to exist for a while on the output capacitor.  Most LDOs would presumably be robust enough to be able to handle this normal-turnoff situation without problem; I just wanted to ensure that this LDO was not an exception.

  • 0 in reply to Daniel Jackson
    TI__Expert 5585 points

    Daniel,

    I've seen if you power down the input at a fast slew rate (> 2A/us), then that charge in the output capacitor has a greater capability of damaging the LDO via reverse current. Slowing down the power down allows the charge to dissipate through the load and/or resistor divider.

    ~ Aaron

  • 0 in reply to Aaron Paxton
    Prodigy 60 points

    Hi All

    This raises a question

    The datasheet does not mention reverse current, for example if a system fault causes the input to drop faster than the output capacitor can discharge.  Neither does it mention a limit on Vout-Vin.  Output Maximum Ratings (section 6.1) are given with respect to GND.  Is there a hazard from reverse current as previously mentioned, and if so, is there a plan to change the datasheet?

  • 0 in reply to Geoff Stokes
    Intellectual 575 points

    All,

    And, if a reverse-current-related (or other) hazard can exist, what workaround is recommended?

  • 0 in reply to Daniel Jackson
    TI__Guru 55940 points

    Hi Geoff,

    As with most LDOs, TPS7A47 was not designed for a reverse current application.  We will update the datasheet to make this more clear.

    Hi Daniel,

    If reverse current is expected, a Schottky diode in parallel will provide an external path for the current.  If your application has enough headroom, you could alternatively place a diode before the LDO's input capacitor.  This will reduce the headroom for the LDO, but in many applications there is still ample headroom to accommodate the dropout requirements of the LDO and the diode drop.

    Very Respectfully,

    Ryan

  • 0 in reply to Ryan Eslinger
    Intellectual 575 points
    Ryan et al,

    What mechanism would result in reverse current flowing through the device, which an external diode would help prevent? If the internal pass transistor were an FET, the FET would clearly support the reverse flow of current through the device. The datasheet shows however that it uses an PNP bipolar transistor, having (presumably) a reasonable Vce breakdown voltage. If so, what mechanism in the IC supports reverse current flow, and why would such reverse current flow tend to be detrimental?

    Also, except in the pathological case of the low-impedance power source being transformed into a low-impedance short to ground (for example), only short-duration capacitor-discharge reverse current flow should ever be possible anyway, which would not seem to necessarily be that much of an issue.
  • 0 in reply to Daniel Jackson
    TI__Guru 55940 points
    Hi Daniel,

    While a FET can technically allow reverse current through a body diode and a PNP can also allow reverse current, the problem is thermals. We do not have the ability to limit current in the reverse direction. Excess current can damage the IC. An external path for reverse current mitigates the risk of damage.

    The risk of reverse current was brought up due to your application having a biased output. A larger concern for reversed current would be if your output was biased to 1V while you did not have an input voltage.

    Very Respectfully,
    Ryan
  • 0 in reply to Ryan Eslinger
    Prodigy 30 points
    Hi All,

    I use TPS7A4701 without protection reverse current.
    Vin = 24V Cin = 10uF
    Vout = 21.5V Cout = 70uF Iout = 0.05-0.6A
    Damaged a few pieces TPS7A4701.
    Update datasheet on protection reverse current, please.

    Best Regards,
    Alexander