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UCC28600 Always at 100% duty Cycle

Vincent Chen90
Prodigy 35 points
Other Parts Discussed in Thread: UCC28600

Hi everyone,

We are trying to build a Quasi-Resonant Flyback converter with the UCC28600.

Input: 80V to 450V DC

Two outputs: 12V @ 0.83A (10W)

At first we tried providing 80V at the input and found out that Vdd rises linearly to about 13V, and the gate would turn on. Once the gate turns on, Vdd quickly drops to zero and the cycle repeats. The nominal load(14 Ohms) receives no voltage.

Later, we decided to debug the circuit by disconnecting the start-up circuit and the load, and provide a constant 13V at the Vdd. The results are below.

Vdd is now constant at 13V and the chip is always on. The yellow channel in the picture is the Gate of the MOSFET, which is 99% duty cycle, which yields no output in the secondary and thus no valley is present to trigger the valley detection logic. Since the Transformer is basically in DC state, a large currents goes through the drain because of the high input voltage. Beyond a certain value, the current becomes large due to the duty cycle and over-current protection triggerred.


Does anyone have any idea about this? Please let us know.

Much appreciated .

  • 0
    TI__Mastermind 31580 points
    Hi Vincent

    Can you check the ploarity of the windings on the transformer? The dot notation in the schematic indicates that all the windings are in the same polarity which is not correct for a flyback transformer. The Main primary winding, pins 1,2, should be of opposite polarity to the the other windings.


    Regards

    Peter
  • 0 in reply to Peter Meaney
    Prodigy 35 points

    Thanks for the reply, please ignore the polarity markings on the schematic as they do not represent the actual polarity. All secondary and bias windings are out of phase with the primary.

  • 0 in reply to Vincent Chen90
    TI__Genius 15910 points

    for your first issue (start up) I suggest you separate the start up resistors (the series resistors you have from the high voltage bulk input to VDD) from STATUS.   You can do this by adding a diode  between STATUS and VDD as shown in my roughly marked up image.  Also shown is an additional bulk capacitor on VDD (10uF should work). This is so the small amount of start up current that VDD needs to start doesn't get diverted into floating gates in STATUSVDD for UCC28600.pdf

  • 0 in reply to Lisa Dinwoodie
    TI__Genius 15910 points
    Vincent,
    Were you able to trouble shoot the board to see if there was anything with the build that would result in 100% duty cycle at max frequency?
    For further assistance we would need more waveforms.
  • 0 in reply to Lisa Dinwoodie
    Prodigy 35 points
    Hi Lisa,

    Thank you very much for the reply, the technique you showed us worked. We also realized the Status pin does not have to be connected if we are not using a PFC controller, so we also tried disconnecting, and it works as well. We have done a lot of testing since then, and we noticed the chip sometimes will not start above 60V-80V, the VDD will rise slowly and it would drop immediately at 15V. The gate would have a very short signal(not enough to turn on the MOSFET), and the process will repeat 5 to 10 times until the chip turns on and start giving the output voltages.

    Moreover, the two outputs change based on the input voltage, even if we designed it to stay at 12V. For example, when the input is increased to 100V, the outputs become 13.6V. The outputs will rise(non-linearly) to 14V when the OVP is triggered and the chip is shut off. We suspect there could be a problem with our feedback network. If not, we might also need to change the CS pin resistors since we believe they also control the power.

    Please let us know what your suggesting is regarding the increase in output voltages when the input increases, our input range is designed to be 80V to 450V DC.

    Thank you very much for your time.
  • 0 in reply to Vincent Chen90
    TI__Genius 15910 points
    Can you tell me what the markings are on the top of the UCC28600 device that you are using?
  • 0 in reply to Lisa Dinwoodie
    TI__Genius 15910 points
    also, what is the primary inductance of the transformer?

    Noise on VDD can be causing the chattering start up so increase the 0.1uF on VDD to up to 2.2uF (sometimes this helps but the ideal value is trial and error).

    For the loop, design it so that at nominal input voltage and 50% load you have a crossover frequency of 2.5kHz to 3kHz and a phase margin of 60 degrees or more. Because of the multiple modes of operation this controller transitions through over the operating range it needs to have room to move around on the Bode plot.