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TPS659037 / POWERHOLD Mode

S.Satoshi
Guru 21685 points

Hi,

My customer plan to use POWERHOLD Mode to receipt ON request. In the Fig 5-21, the POWERHOLD signal is controlled externally, but now they plan to pull GPIO_7 pin up and hold to High level. Can you recommend this configuration? 

Best Regards,

Sonoki / Japan Disty

  • 0
    TI__Genius 16410 points
    Hello Sonoki-san,

    POWERHOLD can be pulled up to a high level. In this case it is recommended to pull up to LDOVRTC_OUT, since this rail is always on.

    If you are powering AM57xx, the power-down sequence of the processor still needs to be met. In this case, the system needs to shut down the PMIC another way, such as the RESET_IN pin. It is not allowed to simply remove power from the PMIC before shutting it off, since then all rails will be disabled at the same time which violates the power-down sequence of the processor.

    Regards,
    Karl
  • 0 in reply to Karl Wallinger
    Guru 21685 points

    Hi Karl,

    Let me ask about power-up and down sequence by using RESET_IN pin with POWERHOLD pulled up to a high level.

    Is following sequence ok for you?

    [Power-up sequence]

    1. Pull RESET_IN pin up
    2. Power-up VCC1、VCC_SENSE、POWERHOLD
    3. Release REEST_IN pin

    [Power-down sequence]

    1. Pull RESET_IN pin up
    2. Power-down VCC1、VCC_SENSE、POWERHOLD
    3. Release REEST_IN pin

    Best Regards,

    Sonoki

  • 0 in reply to S.Satoshi
    Guru 21685 points
    Hi Karl,

    And also, can you comment the minimum duration to release RESET_IN pin after VCC powered up ?

    Best Regards,
    Sonoki
  • 0 in reply to S.Satoshi
    TI__Genius 16410 points

    Hi Sonoki-san,

    Could you please clarify what you mean by "pull RESET_IN pin up" and "Release RESET_IN pin"?  I don't recommend setting RESET_IN high before VCC is supplied, and similarly I don't recommend powering down VCC before setting RESET_IN low.  But you can set RESET_IN high at the same time or after VCC is supplied.  And you should set RESET_IN low before VCC is powered down, making sure the processor power-off sequence completes before power is fully removed.

    > And also, can you comment the minimum duration to release RESET_IN pin after VCC powered up ?

    There is no minimum time for setting RESET_IN high after VCC is powered up.  It can be set high at the same time as VCC (for example pulling up to VRTC) or later.  But I want to mention that the time from RESET_IN until the first rail powers up depends on the delay between VCC and RESET_IN, as described in the wiki post How long do the power sequences take to execute.

    Regards,
    Karl