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TPS659037 / POWER SEQUENCE SELECTOR

S.Satoshi
Guru 21685 points
Other Parts Discussed in Thread: TPS659037

Hi,

My customer is asking about POWER SEQUENCE SELECTOR. We can select three cases as Table 5-13 but I can't find the detailed explanation of Sel_0, Sel_1 and Sel_2. So can you let me know which document we should refer?

Best Regards,

Sonoki / Japan Disty

  • 0
    TI__Genius 16410 points
    Hello Sonoki-san,

    Please check the TPS659037 User's Guide for more information about these settings in each device.
    www.ti.com/.../sliu011

    For both TPS6590376 and TPS6590377, BOOT0 selects between 1.35V and 1.5V for SMPS3 output (DDR supply).
    BOOT1 selects whether RESET_OUT toggles low or not during the warm reset sequence.

    Regards,
    Karl
  • 0 in reply to Karl Wallinger
    Guru 21685 points
    Hi Karl,

    Thank you for your comment, but I can't understand the meaning of Sel_0/1/2. I think we can choose three sequence by BOOT0 and BOOT1 setting. I'd like to know the three sequence pattern.

    Best Regards,
    Sonoki
  • 0 in reply to S.Satoshi
    TI__Genius 16410 points
    Hi Sonoki-san,

    I think that table is not entirely accurate. There should be Sel_0 through Sel_3 - each of those 4 cases can have a different sequence.
    In TPS6590376 and TPS6590377, you can think of it implemented like this:

    Sel_0 = RESET_OUT remains high during warm reset.
    Sel_1 = RESET_OUT toggles low and high during warm reset.
    Sel_2 = Sel_0
    Sel_3 = Sel_1

    Sel_2 and Sel_3 are the same as Sel_0 and Sel_1, which means BOOT0 has no effect on the sequence selection. So BOOT1 effectively selects between the two sequences where RESET_OUT behavior is different during warm reset.

    If you look at figures 12 and 13 in the user's guide from my previous post, you'll see a diagram with the different sequences based on the BOOT1 pin.

    Regards,
    Karl
  • 0 in reply to Karl Wallinger
    Guru 21685 points
    Hi karl,

    Let me ask about RESET_OUT assert. Is RESET_OUT asserted at HWRST reset and SWORST reset?

    Best Regards,
    Sonoki
  • 0 in reply to S.Satoshi
    TI__Genius 16410 points
    Hello Sonoki-san,

    It is asserted low during both HWRST and SWORST (as well as POR). RESET_OUT is asserted low during the power-down sequence, and released high during the power-up sequence. Any reset event which triggers these sequences will assert RESET_OUT low/high.

    Regards,
    Karl