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About Vout stabilization time of LM43602 (SYNC Clock OFF⇒ON)

Guru 19645 points
Other Parts Discussed in Thread: LM43602

Please let me know about Vout stabilization time for below condition of LM43602.

・When SYNC input (EXT clock) changed OFF to ON, what kind of Vout movement?

・And, please let me know about Vout stabilization time on SYNC input:OFF to ON.

Best regards

Satoshi

  • Hello,
    We will get you the data. Please give us your exact conditions. Thanks!

    -Akshay
  • Akshay-san

    Thank you for reply.
    I look forward to your data.

    Customer condition is below.
    ・Vin:15V
    ・Vout:3.3V
    ・Iout:2A
    ・fsw:500kHz or 1MHz
    (・External component is unspecified, anything OK.)
    If the information is insufficient, please let me know.

    Best regards,
    Satoshi
  • Akshay-san

    Sorry for additional question.

    About RT pin and SYNC pin, datasheet written that RT pin(internal) frequency recommend the same as external frequency.
    But regacy DC/DC written recommend frequency: fsw(internal) < fsw(external).
    ※fsw(internal) = fsw(external) × 80%~90% is recommended

    Is it better for fsw(internal) set a little low?
    On the contrary, is there anything wrong the case of fsw(internal) > fsw(external)?

    Best regards,
    Satoshi
  • Hello,

    I have attached bench 'scope shots for the condition mentioned by you.

    15VIN 3V3 2A SYNC TRAN 1MHZ.tif

    As you can see in the above image, there is a very small transition in VOUT and the time to settle also is very small. The free running frequency is 500 kHz and the sync'ed frequency is 1 MHz.  A similar plot with sync clock starting default low is also attached.

    15VIN 3V3 2A SYNC TRAN 1MHZ_1.tif

    For this family of devices the sync frequency can be anything as long as it is in the recommended range. E.g. you could sync a 200 kHz design to a clock running at 2.2 MHz also. The limitations of the sync range would be based on the external component selection such as the inductor and the capacitor. 

    To better explain, consider a 2.2 MHz design. The external components have been sized for this frequency. If this design is now sync'ed to an external clock running at 200 kHz, then the inductor would be very small and the resulting ripple could hit the current limit thresholds and thus cause malfunctions. I hope this helps.

    Regards,
    Akshay

  • Alshay-san

    Yhank you for many information.
    About scope shot of "both 1MHz", SYNC waveform looks reverse polarity.
    Is this the effect of the measurement environment?

    Best regards,
    Satoshi
  • Do you mean default high before sync on? That was on purpose to show the difference. The first plot is with sync default high and the second plot is with sync default low.
    Regards,
    Akshay