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tps24713 DATASHEET

ken holmes
Prodigy 70 points


“9.2.2.2.4 Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. An external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M1 exceeds about 4000 pF.”

WHY would gate voltage overstress be caused by large gate capacitance?  Under what conditions?

WHY would large fault current spikes be caused by large gate capacitance? Under what conditions?

Thanks for your help! 

  • 0
    TI__Expert 5940 points

    Ken,

    I will look into further, and provide partial thoughts here.  For sure, the internal clamp is spec'd at 10uA conditions, with the clamp level near 28v worst case. This is near the 30v max rating on gate.  During fault conditions, trace input inductance will produce a large Vin spike that will induce current due to dv/dt across FET Crss that would have to be clamped.  The larger the FET, the larger Crss generally so I can see this being a factor that the original author had in mind.

    Make sure a stout TVS is in place on Vin to protect against a circuit breaker event and resulting Vin overstress (potentially Vgate also).  The output shottky protects against the likewise negative spike on Vout due to trace inductance at that side.

    Will send another note tomorrow.

    Brian