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RESET_OUT pin of TPS659037

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: TPS659037

Hi,

I would like to know the behaviour of RESET_OUT pin of TPS659037.

When PMIC is in active state, I would like to assert RESET_OUT signal by software for processor.

I think it is possible by using Watchdog timeout. However, SW_RST and DEV_ON also are OFF requests.

So I think Both events also can be used for RESET_OUT assertion.

My question is the below.

1. Can SW_RST and DEV_ON be used for RESET_OUT signal asserting when PMIC is in active state?

2. If both events (SW_RST and DEV_ON) can assert RESET_OUT signal, how is RESET_OUT signal deasserted?

3. If watchdog timer is only solution for RESET_OUT assertion, how is RESET_OUT signal deasserted?

Please adise me.

I appreciate your quick reply.

Best regards,

Michi

  • 0
    TI__Genius 16410 points
    Hello Michi,

    RESET_OUT is on when the PMIC is in ACTIVE or SLEEP state, and off when the PMIC is in OFF state. This is the main way to control RESET_OUT. Let me answer your questions below.

    1. Can SW_RST and DEV_ON be used for RESET_OUT signal asserting when PMIC is in active state?
    [Karl] Both of these will cause the PMIC to sequence all rails off and on, including RESET_OUT. So if it is acceptable to have a cold reset, either SW_RST or DEV_ON will work. Note that SW_RST will immediately power back up, while DEV_ON will only set the PMIC off. You need to set POWERHOLD high or set PWRON low in order to turn the PMIC back on after DEV_ON is set to 0.

    2. If both events (SW_RST and DEV_ON) can assert RESET_OUT signal, how is RESET_OUT signal deasserted?
    [Karl] RESET_OUT is only de-asserted (set high) in the OFF to ACTIVE transition. So in the case of SW_RST, it will be de-asserted as soon as the power-up sequence completes. In the case of DEV_ON, it would be de-asserted only after a new ON request event happens, and the power-up sequence completes.

    3. If watchdog timer is only solution for RESET_OUT assertion, how is RESET_OUT signal deasserted?
    [Karl] Same as #2. Watchdog timer also generates an OFF request, so the PMIC will turn off. After there is another ON request, the power-up sequence will complete and RESET_OUT will be deasserted.

    Note than any OFF request will assert RESET_OUT low, so any event which is in Table 5-10. All of these will have the same behavior that RESET_OUT will be asserted low when the PMIC sequences off, and will be deasserted high when the PMIC sequences on.

    Another option is if you are using TPS6590376 or TPS6590377 with BOOT1=1, then RESET_OUT will be toggled low for 3.3ms during a warm reset. So if you want to toggle RESET_OUT and keep the PMIC on, you could use the NRESWARM pin to accomplish this.

    Regards,
    Karl