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nRESPWRON2 reset hold time in TPS6591133 for DM8148

Madhura Shetty
Intellectual 810 points
Other Parts Discussed in Thread: TPS65911

Hello,

We have designed a DM8148 custom board with FPGA . DM8148 will be booted from the image stored in the NAND flash. After configuration of the FPGA it will issue a reset to the processor. DM8148 is powered from TPS6591133 PMIC which gives nRESPWRON2 once all the power rails from PMIC are stable. Attached POR scheme of the processor.

Concern:

We observed that while powering on/off the board or by re-configuring the FPGA , NAND image is getting corrupted i.e DM8148 processor is not booting from working image from the NAND instead booting from Golden image. We checked for power dip and it is fine. This issue is observed randomly in most of the boards.

We suspected the reset and did multiple experiments and concluded thet nRESPWRON2 is not holding reset of DM8148 for sufficient time which inturn causing inconsistency in booting.

Please let us know for how long TPS6591133 will hold the reset for DM8148 (Time). Is it possible to change or adjust the reset time of nRESPWRON2 signal?

Regards

Madhura

  • 0
    TI__Genius 10885 points

    Hi Madhura,

    I found the following excerpt from the datasheet:

    6.3.3.4 NRESPWRON, NRESPWRON2
    The NRESPWRON signal is used as the reset to the processor and is in the VDDIO domain. It is held low
    until the ACTIVE state is reached. See Section 5.23.1 to get detailed timing.


    The NRESPWRON2 signal is a second reset output. It follows the state of NRESPWRON but has an
    open-drain output with external pullup. The supply for the external pullup must not be activated before the
    TPS65911 device is in control of the output state (that is, not earlier than during first power-up sequence
    slot). In off mode, the NRESPWRON2 output has weak internal pulldown.

    What is supplying VCC_DM8148_3V3?

  • 0 in reply to Richard Solarski
    Intellectual 810 points
    Thanks Richard,

    VCC_DM8148_3V3 is a supply from a switch which is enabled from TPS6591133-PMIC to follow the recommended power on sequence for the DM8148 device.
    From datasheet what I understood is the reset hold time for nRESPWRON2 signal is 32ms. Please confirm the same. In that case this time duration is less for our application. Is there any options to increase the timing by writing some registers?

    Regards
    Madhura
  • 0 in reply to Madhura Shetty
    TI__Genius 10885 points
    Hi Madhura,

    Yes it will be around 30ms, and outputs assigned to time slots cannot be altered, so there is no way to increase this delay through internal registers.

    If nRESPWRON needs to be extended beyond the assigned time slot, an external delay circuit would have to be implemented.