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2nd Question for TPS65198

Eric Kim1
Prodigy 170 points
Other Parts Discussed in Thread: TPS65198

Hi Team,

My customer have a question for the TPS65198 operation by the input signal format and and want to know  the attached signal format will generated the expected output or not.

And I have a question in myself, it is not customer's question.

Is there any timing criteria between MCLK and GCLK as described on the attached file?

Thanks an regards,2nd Question for TPS65198 Input signal format.xlsx

  • 0
    TI__Intellectual 1065 points

    Hi Eric,

    Please refer to Figure 23 of the TPS65198 data sheet.

    The input sequence at the start of the frame is

    • GCLK rising edge
    • GCLK rising edge
    • GCLK rising edge

    After three GCLK rising edges, the level shifter starts the middle of the frame and the input sequence is

    • MCLK falling edge
    • GCLK rising edge
    • MCLK falling edge
    • GCLK rising edge
    • ..
    • ..
    • MCLK falling edge
    • GCLK rising edge

    At the end of the frame, the input sequence is

    • MCLK falling edge
    • MCLK falling edge
    • MCLK falling edge

    You must make sure that the input signals are as described above. In the middle of the frame, the falling edge of MCLK must always be finished before the rising edge of the next GCLK occurs. We have not specified any timing requirements in the data sheet, but the logic in the TPS65198 is quite fast, so I would expect that the device will operate correctly down to a delay of a few nanoseconds (I didn't test this, it's just my engineering judgement).

    The rising edge of MCLK does not affect the output sequence, it only starts the gate-voltage-shaping function.

    Let me know if anything is still not clear – it's quite hard to describe this function :-)