Application question of TPS2553/2553-1

Please find reply inline:

               1)  Overcurrent Deglitch is available in the both of asserting and de-asserting the /FAULT , right ? Yes, for both OC and reverse voltage faults.

               2)  Deglitch is the delay time from detecting the overcurrent to asserting the /FAULT signal ,right ? Yes. When the current is exceed the current limit and then go down below the current limit in the period of 7.5ms deglitch time , the /FAULT will still be asserted ? Yes

               3) The Vout will go down near the zero when in the constant current mode of 2553, could you please see the test waveform below , the /fault is asserted, but the Vout is no changed , could please explain that? Refer to figure 4. Vout may not go all the way to zero for soft overloads. What is your current limit setpoint?

               4)  The TPS2553-1 will be latch-off and turn off if in the current limit,  turn off means open the switcher and no output current and voltage ,right? Yes.

Hi  Eric:

           Thanks for your reply.

           For question 3) , the setting resistor is 150kOhm , so the Ilim(nor)= 175mA.  In sight of the plot , the /fault will be asserted so long as the current reach the current limit no matter the soft or the heavy overload , right ?

           One more question , it is a valid overcurrent event so long as its duration is reach 2uS (tios) ,right?

Yes, /FLT will assert under any current limit condition.

Tios is a spec that quantifies how fast the switch can react to a hard overload condition and fully shut down the current. See figure 3 for an example of the behavior.