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A question about the OTG funtion in bq24195.

user4233221
Prodigy 130 points
Other Parts Discussed in Thread: BQ24195

Recently, I am designing a Power Bank.

From the datasheet,  I learn this chip (BQ24195) works as the following process after the power plug in:

1. The D+/ D- detect whether the power is from the USB or not (from an adapter).

2. Detect the voltage on OTG.

Thus, there are following combinations:

     PORT             OTG                  I(limit)                 BOOST (determined by OTG and Register)

1. USB                LOW                 100ma               CAN'T be used

2. USB                HIGH                500ma               CAN be used

3. Adapter(>=5v)          LOW                 User's config     CAN'T be used

I can understand that, the OTG will be low when adapter is plugged in, because the voltage >= 5v, thus the Q3 in the schematic will must be opened. 

Yet my question is, normally, the usb port is also 5V, thus, the Q3 will also be on, after USB Port is connected,  which means that's the case 1. Then the input current is limited to 100ma.

I mean how to use USB port to charge the battery, or a power bank?

Another problem of my circuit is that the current is only 0.09A after I connect the circuit:

From the circuit I summarize the cases that will lead the input current to be limited to 100ma:

1. 0.5 sec timer expired in DCD (This must after the primary detection, I think. I mean this condition will not happen if the chip already know that the power supply is an adapter but not a USB port.)

2. USB HOST and OTG low (HIZ)

3. System rail below 2.2V (Dose this system rail refer to Vsys on SYS pin ?)

4. HIZ

I power my circuit by a DC Power Supply, So, from my analysis, it shouldn't be case 1 and case 2. The Vsys on SYS pin is 3.62 V, so it shouldn't be case 3. Only left case 4. Why the current is only 0.09A? Does it enter HIZ? WHY?

  • 0
    TI__Mastermind 31580 points
    Hi

    Your post is in the wrong forum, I have moved it to the battery management forum.

    Regards

    Peter
  • 0 in reply to Peter Meaney
    Prodigy 130 points
    Thank you very much!
  • 0 in reply to user4233221
    TI__Expert 8230 points
    Hello,

    I'm trying to understand your question better. Are you inquiring about how the D+/D- detection works and how it's used to set the input current limit, or how to enable OTG?

    Input current limit set by D+/D- is different than the OTG output current limit.

    If VBUS is less than VBAT+VSleep (typ 80mV, max 120mV), OTG cannot be activated. In your example, if you have the adapter plugged in, that means that Q3 will be turned on and the OTG pin will be held low, disabling the OTG functionality. This way, you won't be trying to charge and discharge at the same time.

    For power bank applications, the boost output current is provided from the PMID pin. Please note that there is no boost current limit setting when the boost current is sourced from PMID pin, hence it is important not to overload the boost current under this condition.

    The HIZ + 100mA input current limit you are observing is most likely the scenario where the input source is detected as a 100mA USB host and the battery voltage is above the VBATGOOD threshold, at this point, the charger device enters HIZ state to meet the battery charging spec requirement. Please refer to section 8.3.1.3.3 to 8.3.1.3.5 for full details on the D+/D- detection scheme.
  • 0 in reply to Fernando Lopez
    Prodigy 130 points

    Thank you very much for your reply. It helps me solve most of my problems. Yet, I still have a small question:

    From the table, when D+/- Detection is USB HOST and OTG = HIGH, the input current limit = 500mA. How this  case can be possible? I mean, when this chip is connected to USB Supply, normally 5v,  Q3 will be on, then the OTG = LOW. It seems it's impossible that the OTG is HIGH when we use USB port.

  • 0 in reply to user4233221
    TI__Expert 8230 points
    Hello,

    Couple things to notice: the bq24195 is a device intended to be controlled via I2C; also the schematic presented on the datasheet is only one example of an aplication implementation.

    In this example, if we are trying to control the input current limit in a standalone configuration using the external Q3 FET, the USB host will be limited to 100mA. In this example, the charger is controlled by a host as well, which can modify the input current limit registers if desired, for example to 500mA.

    Hope this helps.