Hi,
We are planning to use LP2951-50DRGR in our design. In the device datasheet, it is mentioned that there is minimum output capacitance requirement with ESR range for stability of the LDO. I have provided LDO requirement for our product, Input/ Output capacitors chosen for our design below. Could you please confirm whether these capacitors satisfy LDO Input/Output capacitance requirement?
Design Requirement, Capacitor values data:
1. I/P voltage: 24V
2. Output Voltage: 5V
3. Load current: 6mA to max 60 mA.
4. Input Capacitor: P/N: GRM31CR61H106KA12L. 10uF ceramic capacitor (placed approx 2 inch away from LDO IC)
5. Output capacitor: P/N: TPSB106K016R0500 10uF tantalum capacitor (ESR value: 0.5 Ohms @ 100 kHzResonant freq: 1 MHz), further there are 6 x 0.1uF bypass capacitors placed near different Digital ICs (Loads).
6. I am unable to find ESR curves showing LDO stable region in Typical characteristics section of datasheet.