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UC3525 PWM Sync Problems

Charles Barnett
Prodigy 40 points

I am trying to get a UC3525 PWM chip to sync. Need to know correct method. I have been applying ro rhw aync pin 3 a 3v positive going pulse that is 0.7 us wide running at 40 kHz so I can get 20 kHz at the outputs. This makes the outputs fall into sync but distorts and reduces the pulse width to less than their 50% max.Maybe I need to keep pin 3 high and pull it low for the 0.7 us pulse?

  • 0
    TI__Mastermind 31580 points
    Hi Charles,

    The first suggestion I can think of is to reduce the pulse width to less than 100ns to see if there is a relationship between the sync pulse width and the distortion of the PWM pulse width. I assume the sync frequency is at least 10% higher frequency than the free running frequency of the IC?

    Regards

    Peter
  • 0 in reply to Peter Meaney
    Prodigy 40 points

    Hello and thanks for your reply. In agreement to what you say above about the 10% higher frequency here is what I have found and this may help someone else. The problem is that I had both Rt & Ct  the same in the master and slave because I wanted both PWMs running at the same frequency. The instructions say to make the Rt Ct of the slave 20-30% lower in frequency than the master. This did not make sense because I wanted both PWMs running at the same frequency. I had both PWM running at 40 kHz clock frequency but still had the distortion (reduced pulse width) in the slave outputs. After adjusting Rt on the slave which would have made it run lower in frequency if it had been running by itself, the distortion went away. Even though the RtCt combo is a longer time constant in the slave, both PWM are running at the same frequency as the master.