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TPS65083x Comparator logic implementation for Skylake

Roshan Dsouza25
Prodigy 90 points

Hi,

In the TPS65083x reference design, comparator D logic is bit confusing.

VSD pin is connected to VCCIO, ENG is connected to SLP_S3# and PGD is used to enable VCCIO load switch.

My question, how the PMIC will enable PGD since VSD is connected to VCCIO which come after PGD. 

OR please let me know whether my comparator logic understanding wrong?

  • 0
    TI__Genius 16870 points
    Hi Roshan,

    In this device the PGD does not indicate the power good of the comparator D but, rather it is the enable for VCCIO rail. Just the name of the pin stayed the same as PGD. The PGD goes high after the END input goes high unless I2C tells the PMIC to disregard the END or to override the END input with an I2C enable.
  • 0 in reply to Michael Green
    Prodigy 90 points

    Hi Michael,

    Thanks for your inputs. As per the PMIC design guide

    "For the 8 comparators on the device, (A - H), the VSx signals can be configured as needed for the application in use. The corresponding ENx pin enables the comparating function on the VSx pin with the output logic HIGH or LOW on the corresponding PGx pin."

    I would like to know the use of VSx pins and how it is implemented in the reference design?

    Regards,
    Roshan Dsouza

  • 0 in reply to Roshan Dsouza25
    Prodigy 90 points

    Hi Michael,

    Could you please suggest on this ?

    Regards,
    Roshan Dsouza

  • 0 in reply to Michael Green
    TI__Expert 3245 points

    Hi Michael G,

    Can you please elaborate on the following:

    If we see the comparator B implementation in the reference design for sky lake,

    • VSB is connected to V1.8U_2.5U and ENB is connected to SLP_S4#
    • PGB is connected to the enable pin of V1.8U_2.5U load switch.
    • V1.8U_2.5U is enabled after PGB (V1.8U_2.5U_LSW) goes high.

     

    It's like the load switch output is used to enable the load switch.

    My question is how will the comparator monitor the V1.8U_2.5U rail? Whether during start-up it will ignore the VSB pin and drive the PGB signal high when ENB signal goes high?

    Same question applies for Comparator D.

    Note that we are planning to design the board without EC. So all the default settings of PMIC will be used.

    Thanks,

  • 0 in reply to Michael Raleigh
    TI__Genius 16870 points

    The comparator does not ignore the VSB input, it simply re-purposes PGB to not be a power good and only be an enable for V1.8U_2.5U. Just think of it as the power good signal from comparator B does not come out on a pin and is only used internally.


    ENB starts the comparing of the VSB input and drives PGB high if the I2C registers allow it, which by default they do. There is a 10ms delay on the power fault so, the V1.8U_2.5U has 10ms to rise up to regulation without the fault being triggered. After the 10ms fault condition can be triggered if VSB is out of range for > 30us.
    I2C can override any of these commands including, faults, power good trees, and enables/disables.

  • 0 in reply to Michael Green
    Prodigy 90 points

    Hi Michael,

    Thanks for the details on comparator B. I was always thinking the comparator output will come out vai PGx pins.

    As per reference design, for comparator E, VSE is connected to V3.3S and PGE is used to enable V3.3A_PCH rail and ENE is connected to SLP_SUS#.

    Here V3.3S may come after 10ms from PGE high so, it will it trigger any internal fault condition. Also during sleep mode, V3.3S will be switched off since it is controlled using SLP_S3# signal but  V3.3A_PCH should be on.

    Regards,

    Roshan Dsouza