BQ76920 Smokes Out If BATT+ & BATT- Are Connected Before Cell Lines

Hi Robert,

This experience is completedly unknown and unexpected.  Connection of BATT- then BATT+ on a bq76920 should be a best case situation.  The part should see BAT applied with respect to VSS and all inputs should distribute at nominal voltages between these. Outputs should be low until the part is awakened.  The only case of parts smoking I can recall at this point is when a user's LED supply transistor shorted forcing BATT+ onto the CAP pin.

Since you had good results in prototyping, inspection of the assembly fixturing and tooling for unexpected conduction paths or voltages may be a good first step and something you have already explored.  If your schematic is much like the EVM, the IC is isolated from the pack voltages by resistances, has filter caps and no high current to the part is expected.  Inspection of the production lot components and installation is certainly also a good step.  If your design has a transient limiting circuit like D1 on the EVM that should limit the power transient.  The hold up diode (D2) has a peak detectior effect, you might check if it could pump up the voltage faster than R3 can bleed it off.

Inspection of a damaged board may give some indication of the current path and clue as to why the production result differed from prototyping.  In the case noted above the bq769x0 package was blistered at the CAP1 pin.   Look for discolored pins or damaged filter components.  If you use a similar transistor on the CAP pin it may be a place to start, the EVM has no resistance in that path other than the transistor.   You might look at voltages to the IC pins during connection, check for signals coupled through your uC to the bq76920.

Connecting BATT-/BATT+ provides a 15 to 20V step to the electronics vs a 3 to 4V step when cells are connected sequentially bottom up, something on the production board assembly may not tolerate that step as well as the prototype.

If it is helpful we can discuss offline or have a NDA setup if needed.  In the end the community may be interested in the solution and learning from what we can share.

Hello,

Thanks for the prompt reply and your suggestions. We'll do some more diagnostics and see if we can get to the bottom of it. The passives & boards (we've blown about 5-7 testing, and it is pretty consistent) don't exhibit any obvious symptoms of over-current, but some measurements should show if they have deviated from their expected values.

The damage on the IC is consistently on the bottom-left side (pins 6-10) which is where BATT+ and REG pins are found. We do have REGSRC running to BATT+, but because the same voltages/current are available when the cell lines are connected as when the +/- lines are, problems with the linear reg. is likely a red-herring. 

One other thing; if we assemble the boards, then remove the cell lines while powered, nothing burns out. We first get an OV trip from the AFE (expected?), then an XREADY fault (also expected?), but everything still seems to function normally. It does appear as if the initial power-on condition is the only point of failure for having only the B+ & B- lines connected..

I will see what we can do to provide some more information and if the problem is resolved, we'll be sure to let everyone know what has gone wrong. Every other feature of the chip has performed exactly to specification, so this has come as a late & unexpected surprise.

Thanks again.

Robert,
please send me the actual hookup ( schematics) of the BAT+ to the REGSRC. use email , 

Hi Vish,

Thanks for your help and suggestions. We've sent the schematic to you over the weekend via email and await any input. So far several modifications have been tested to see if they ameliorate the problem but we have not been able to isolate it.

Notably, we're not encountering this failure in all instances. After testing, we've found this occurs in only about 20-30% of the boards we have assembled. 

Please let us know when you have any thoughts.

Thanks again.

Hi Vish,

Thanks for your analysis. We can confirm that 100 Ohm between REGSRC & VBATT+ seems to resolve (30 units tested, no failures).

Really appreciate your attention in this matter and we'll be sure to bias towards TI chips for all our applications following such timely support.

Cheers,

Robert

Out of curiosity, is there any explanation why hooking up the cell lines would prevent this failure? It tested out fine 100% of the time for ~100 units. Quite literally we could plug the cell lines in on a unit repeatedly and have everything be fine and then only BATT+/- and have the IC pop straight away. In the end, a 5S (18-21V) battery would be connected between BATT+ (REGSRC in this incorrect design) and VSS in either case. The cell lines would have the current carrying capacity to effect the same damage to the IC, so why didn't we ever see it occur?

Please let me know if you have a chance to consider. Thanks again.