UCC28700: start-up without full energy transfer

Rob,

There is a lot of info here to analyse. Unfortunately, it would be helpful if we could also see the schematic, with values, turns ratios etc. Would it be possible to post that too?


From the info above, here are my various comments and observations (not in any particular order):

- Since the UCC28700 operates in valley-switching mode, it attempts to always switch on a resonant-ring valley, depending on the line/load/output voltage conditions - so the earliest it can switch is on the first valley (in QR mode), or more usually a later valley to hit the target freq set by the modulator (datasheet fig. 15), or sometimes if the load is light and operation is very DCM, it's not possible to valley switch since they have been damped and died away.

- During startup (or any other time) it's not possible to force a fixed freq, since this could allow the power stage to go into CCM - or more correctly, the DCM-only/valley-switching mode of operation will dictate the freq so as to avoid CCM.

- During startup, since Vout starts at zero and ramps slowly, the Flyback reset interval will be quite long initially, so the switching freq will be lower as the controller looks for the first valley to start the next cycle. s Vout increases, the Flyback reset interval gets shorter, the first valley occurs sooner, and freq then naturally ramps up.

- During startup, once Vout has risen sufficiently, the control loop will operate in CC-mode, regulating the Flyback reset interval Dmag duty cycle to Dmagcc (42.5%) while delivering constant maximum Ipk (750 mV). The switching freq will then vary as Vout rises. In CC-mode, a constant average output current is delivered to the output caps/load, so this should give a well-controlled linear ramp up of output cap voltage.

- Looking at the first plot above, one can see that there is a significant overshoot in VDD as Vout ramps up, yet Vout does not overshoot. This tells us that the primary peak current is large (due to the 1-nF CS pin cap), and also the aux winding leakage inductance is probably large. If the CS pin RC filter is excessive, this will result in higher actual peak current vs the programmed peak current at the CS pin. This will then force the control loop to run at lower freq, since the energy per cycle is higher than it ought to be. The higher peak current will also lead to more energy stored in the leakage inductance, which in turn will cause the Vdd rail to pump up to a higher level - as can be seen in this case. Very often, a small-value resistor is used in series with the aux winding diode (1-10 ohm) to limit the over-charging effect on Vdd due to the aux leakage inductance. Not too, that the RC filter on CS will have a more pronounced effect as input voltage rises - since the di/dt of the current is steeper at higher voltage, the RC delay results in more overshoot.

- For the second plot, with the smaller filter cap on the CS pin, it looks like the Vdd rail falls too low while Vout is ramping up - there is just not sufficient energy storage in the Vdd cap. The next plot also confirms this. With smaller CS filter cap, peak current is lower (closer to what it ought to be), so the output cap ramp rate is slower, so the Vdd needs to sustain the IC bias power for longer. Moreover, the lower Ipeak means there is less parasitic energy storage in the aux leakage inductance, so again the Vdd rail replenishment from the aux winding takes longer.

- From the datasheet, eqn 13 estimates the required CVdd size based on Cout and the Iocc charging current into Cout - assuming there is no load at startup. From eqn 13, since the average charging current into the output cap (Iocc) is regulated to a constant, this Iocc value, the size of output cap, and the max load that can be present under startup, are the limiting factors that dictate the required CVdd size - the Fsw does not come into the eqn at all, so increasing the Fsw during startup would not help, except for effects of parasitics (leakage) or non-idealities (peak current overshoot).

- For your second plot above I assume that there is no output load or very little, since the system succeeds in starting at the second attempt - Vout "staircases" up over a few attempt. If there is enough load to discharge Cout in between startup attempts, then it would not be able to start.

- If the required CVdd is too large to meet your startup requirement, the startup resistor would need to be reduced to compensate. If the reduced startup resistor leads to higher standby power than can be tolerated, maybe you could consider one the parts in the family with integrated HV startup, e.g. UCC2871x or UCC28730.

- One other point to note is the amount of required output cap is dictated more by loop stability than by energy storage. As Vout goes up, the required size of Cout for stability may not drop as rapidly and C*V^2 energy storage might imply. If you take a look at the UCC28730 device (more recently released part in the family), there is a an eqn 22 for min Cout required for loop stability - Cout >= (Kco * Iocc ) / (Vo * Fmax), where Iocc is the constant current output limit, Fmax is the max operating frequency at the CV/CC operating corner, and Kco is a constant that depends on the chosen IC in the family. For the UCC28700, Kco is ~400.


I hope all this info is helpful. As noted above, we can help review the design more thoroughly is that helps, but we would need to see the sch, values, turns ratios etc.


Thanks,
Bernard