LM5116 Schematic review

Hi
Can anyone help me to review the schematic?

Thanks in advance.

pradhan

Hi

Please refer my comments below.
-Place C_vin as close to the IC
-Populate C_uvlo if you wnat a hiccup operation.
-Please ground VCCX pin if it is not used.
-Reserve foot prints for RC snubber at SW node.
-Reserve a foot print for a gate resistor at HO
-MOSFET voltage rating should be at least 10V higher than max Vin.

I didn't look at the component values. Please refer the quick start (www.ti.com/.../lm5116-5116wg-25116design-calc) and select component values

Regards,
EL

Dear Eric Lee

We have done the final layout and schematic.

Attached is the schematic and layout.

Kindly help to review and help us with your feedback.

Awaiting for your kind response.

thanks and regards

Pradhan

TK_CH_SCH_LM5116.pdfTI_REVIEW_LAYOUT.zip

Hi Pradham,

Eric Lee is out of the office until 8/8/16. You may want to wait for his inputs.

I have reviewed only your latest schematic. It appears your schematic is similar to the LM5116 "8.2 Typical Application". I would recommend checking your component values using the Quick Start Calculator recommended by Eric Lee. My concerns are:
1) VCCX should be grounded if not used.
2) RRAMP is not required if VOUT < 7.5V (as stated in the Quick Start Calculator).
3) Your IOUT = 5A. This changes the inductance and Rsense calculations vs the IOUT=7A used in "8.2 Typical Application".
4) When using the Quick Start Calculator make sure to select DEMB "Required" in Step 10, VIN Undervoltage Shutdown "Yes" in Step 7, Current Sense Method "Rsense" in Step 2.
5) If hiccup mode is required, select a Cft.

Regards,

Raymond Beahm

Dear Raymond

Thanks for your quick response. I will go through it and will revert back.

I also attaching the Layout file again. Kindly help to give your valuable comments.7384.TI_REVIEW_LAYOUT.zip comments.

Thanks and regards

Pradhan

Dear Raymond

Awaiting for your feedback on Layout review.

Thanks in advance,
Pradhan

Hi Pradhan,

I reviewed your layout.
1) I would recommend referring to the LM5116 section "10 Layout" and "10.2 Layout Example", specifically placing the VIN, GROUND and VOUT as shown, if possbile.
2) Is there a missing via connecting to Q1 (TOP) from the POWER (inner layer)? I cannot tell from the .pdf. There are via connections to C2 and C3 on top, left side between TOP and POWER.
3) On the "GND" layer there are several overlapping connections to "GND" with VIA feedthru exclusion mask. I am not sure if this was intentional.
4) I did not review the layout or connections to the other devices.

Hi Raymond

Thanks for your valuable suggestions.

 

Please find attached updated schematic of LM5116. Also attached 74V@5V design from WEBench.

As per your suggestion I have done all changes in my schematic, I also refer my design with  WEBench tool.

Kindly review it and give your suggestions.

Regards

Pradhantk_ch_sch_comfort_heater_1_8_16.pdf`webench_design_4508235_134_569890674.pdf

Dear Raymond

Awaiting for your valuable inputs on my earlier post for the schematic review.

Also in addition Please find attached zip folder of updated Gerber File of LM5116 Voltage regulator.

We have done placement according to Layout Guide lines of LM5116.

Also done changes suggested by you.

Kindly review the updated Gerber file and reply me ASAP.

Thanks in advance.

PradhanUpdated Layout_LM5116.zip

Hi Pradhan,

I have a few suggestions for the two LM5116 schematic layouts that were provided. Please also take a look at the LM5116 EVM as a reference layout. Here is a good article that covers some basics on buck converter layout. Please also refer to the layout section in the datasheet for a few layout notes.

74V to 5V @5A

• Reduce the HO gate driver loop size to reduce the chance of large voltage spike on the HO gate driver
  • Move the VCC (C7) capacitor to the other side of the LM5116
    • This will reduce the trace length and the number or vias needed reducing any parasitic inductance
  Move the Boot Diode (D3) to the other side of the LM5116
  • This will reduce the trace length and the number or vias needed reducing any parasitic inductance
  Move the Boost Capacitor (C8) as close as possible to the HB pin,
  • This will help minimize and ringing by reducing any parasitic inductance
  • It is okay to route the HO signal under this capacitor as long as the HO trace is protected by a ground lay
• • Route the SW pin to the Source of Q1  being used as a return path. Route the HO pin to the gate of Q1

• • Look at the LM5116 EVM for example.
  • This will also help to reduce and ringing and minimize some EMI effects.
  • SW pin should be a trace to Q1 source
  • Keep HO and SW traces as shotr as possible

• Kelvin sense the current sense resistor to CS and CSG pins
  • CSG pin should be routed to the ground side of R8 not direcetly to the PGND pin. This will help to reduce any noise seen on the current sense signal
  • The CS and CSG traces should be run parallel to each other to reduce parasitic inductance
  • Please reference the LM5116 EVM layout
• Have a separate AGND and PGND and connect them both to the DAP of the LM5116
  • AGND signal are noise sensitive and should be connected here to reduce any amount of ground bounce noise
    • These signals terminations include RAMP, RT, SS and FB
  • Can't tell currently, but there should be a large pad of copper under the LM5116 DAP so that it can be soldered to this
    • This will help with noise as well as help with thermal dissipation
• Move components closer PINs to reduce noise as there are noise sensitive signals
  • RAMP capacitor
  • FB resistors. Move R9 closer to FB pin.
  • RT resistor
  • Compensation components as close to FB and COMP pins
  • VIN needs to have a capacitor closer to the pin to help reduce noise

74V to 48V @4A. Many of the same issues as the other circuit

• Reduce the HO gate driver loop size to reduce the chance of large voltage spike on the HO gate driver
  • Route the SW pin to the Source of Q1  being used as a return path. Route the HO pin to the gate of Q4
    • Look at the LM5116 EVM for example.
    • This will also help to reduce and ringing and minimize some EMI effects.
    • SW pin should be a trace to Q1 source
    • Keep HO and SW traces as shotr as possible
  • Pull the boot diode and boot capacitor closer the HB pin
    • Same idea as the above comments.
• Kelvin sense the current sense resistor to CS and CSG pins
  • CSG pin should be routed to the ground side of R19 not direcetly to the PGND pin. This will help to reduce any noise seen on the current sense signal
  • The CS and CSG traces should be run parallel to each other to reduce parasitic inductance
  • Please reference the LM5116 EVM layout
• Have a separate AGND and PGND and connect them both to the DAP of the LM5116
  • AGND signal are noise sensitive and should be connected here to reduce any amount of ground bounce noise
    • These signals terminations include RAMP, RT, SS and FB
  • Can't tell currently, but there should be a large pad of copper under the LM5116 DAP so that it can be soldered to this
    • This will help with noise as well as help with thermal dissipation
• Move components closer PINs to reduce noise as there are noise sensitive signals
  • RAMP capacitor
  • FB resistors.
  • RT resistor
  • Compensation components as close to FB and COMP pins

Hope that helps.

-Garrett

Dear Garrett

Thanks so much. I will go through it and update you.

Thanks once again

Pradhan