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TPS650842 questions

daniel
Genius 5095 points
Other Parts Discussed in Thread: TPS65094

Hi,

I have some question about TPS650842, please help, thanks.

1. Besides this project, what project or other end customer use TPS650842 also?

2. How many layer PCB dose TPS650842 require?

3. For INTEL S3/S4 suspend mode, does SW need to send command to TPS650842?

4. Does TPS650842 support 2-ch DDR?

 

thanks

 

daniel.chung@wpi-group.com

  • 0
    TI__Genius 17380 points
    Hi Daniel,

    1. The TPS650842 for Intel Braswell is used in a variety of applications by several end customers. In particular, it is found in several Ultrabook / AIO / tablet designs, a couple of storage devices, and a variety of more unique cases.
    2. 4 Layers is typically the minimum. The EVM is done in 6 layers to maximize performance.
    3. The SoC has dedicated S3 and S4 pins which connect to the PMIC's SLP_S3B and SLP_S4B pins to enter/exit sleep states, so no I2C writes from SoC to PMIC are necessary.
    4. The TPS650842 uses a controller with externally set current limit resistor for the VDDQ rail, so high currents are possible. The VTT LDO is specified up to 500 mA for this application, but can go higher (see TPS65094 datasheet for example). ILIM for VTT for this OTP is set to 950 mA, but could be extended if sufficient business case for an OTP spin exists.