Hi team,
In UCD3138 Technical Reference Manual document，page 397 has below description:
"The clock then runs through a prescaler. The prescaler is controlled by an 8 bit register. Register values
from 0 to 255 correspond to dividing the clock by 1 to 256."
In page 406, Table 11-2 also show below description:
PRESCALE reset value 0
Defines the prescaler value used to select the 24-bit counter resolution. The
minimum divider ratio is 4, prescaler value less than 3 defaults to 3.
The questions is the divider clock of the T24 is 1-256 or 4-256 ?
Thanks.
