TPS65400 External Clock Synchronization

Hi Kobayashi-san,

Typical high voltage is 3.6V, typical low voltage is 3.3V, low voltage is 0V.
thanks!

Eric-san
Please see section 8.3.5 "Clock Synchronization" of DS.
It's described that the typical trip level of the synchronization terminal is 1.5 V.
Please let me know that min/max of that trip level.

Regards,

You can refer to DS's description, the high voltage is better to 2.5V to 3.3V.

thanks!

"The typical trip level of the synchronization terminal is 1.5 V. To ensure proper
synchronization and to avoid damaging the IC, the peak-to-peak value (amplitude) should be between 2.5 V and
VDDA. The minimum duration of this pulse must be greater than 200 ns, and its maximum duration must be 200
ns less than the period of the switching cycle"

No, my question is Min/Max value of the Trip Level.
I think your answer is recommended amplitude of external clock signal.

When inputting a clock by an AC couple as shown in the Fig.14, the amplitude of pulse on the RCLOKC_SYNC terminal will be half of plus and minus.
The negative side is clamped by the internal diode and the positive side will be half of amplitude .
I think that when using a clock of 2.5Vpp pulse, it doesn't reach the typical trip level (1.5V).
Is my understanding right?

Eric-san
Please give me your answer.