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LM5056 SPI bus impedance when powered down

Timothy Starr
Expert 2445 points

Hello-

We plan to power down our 5V VDD pin on the LM5056 on occasion, but would like to still talk to other 3.3V device on the same SPI bus. Will the LM5056 SPI pins go into high impedance?

How about at least the input pins? I'm thinking we can put a 3.3V tristate buffer on the SDAO pin to avoid bus contention in this state.

Thanks and Best Regards,

-Tim Starr on behalf of OA@CE

  • 0
    TI__Expert 5940 points

    Tim,

    I believe being the LM5056 is PMBus compliant, I believe it would be a requirement to not interfere with the bus when powered off.  I have not personally tested this.  You can check the PBMbus 1.2 standard (Google this) and double check. 

    Brian

  • 0 in reply to Brian Daugherty
    Expert 2445 points

    Hi Brian-

    This is not an acceptable answer. We need to know before we build our circuit board if our circuit is going to work. Please check with the designers of the part, and/or test the part. The PMBus standard is not the determining factor, no matter what it says (or in this case, what it does not say).

    Thanks and Best Regards,

    -Tim

  • 0 in reply to Brian Daugherty
    TI__Expert 5940 points
    Tim,

    The LM5056, like many TI products, is designed to PMBus and SMBus standard compliance. It is high Z as specified in PMBus 1.2 specificaiton, part 1, paragraph 5.2.8, page 16. This is a requirement for all such devices. This is also stated in SMBus specification. If you have any issues with this operation, please inform your local TI Sales office. To date, I have never had a single non-compliance issue in this regard.

    Brian