TPS50860 Control Inputs OTP Settings Eval board vs. Default OTP Settings.xslx

Hi Guenter,

My apologies that this is not well documented yet, we will be improving the OTP explanation as we release additional OTPs.

The Alternate Voltage Pin applies to whether the BUCKx_VID or BUCKx_SLP_VID settings are used. For example, BUCK4 in TPS650860 is still enabled/disabled by CTL2. With CTL3 Low, BUCK4_VID settings are used, while with CTL3 High, BUCK4_SLP_VID settings are used. The same would be true for BUCK1 + CTL6, but the BUCK1_SLP_EN bit is set to 0 in the TPS650860 OTP so BUCK1_VID is used unless that bit is changed to '1'.

Regarding customer OTP programming, it is not currently offered. We are investigating the possibility but are currently looking on a case by case basis to validate the opportunity investment as programming is still rather complex. Would you be interested in the feature for initial debug / OTP generation only or would doing the programming in MP be a viable strategy as well? If so, would you be doing it on board or using a gang programmer with socket?

Hi Kevin,

thanks for the quick answer, SLP_VID usage is understood now. Although I 'd like to have some more detailed Information about OTP details, I'll wait for datasheet updates and continue with what I have. I'll still be exploring if/how the 650860 or the 6508640 fit our scenario. If these versions don't fit, we need customized OTP.

Customer OTP during development and debug would be quite helpful to get done quick enough as we are under time pressure. Later on, factory programming may more suitable, but that's only a guess. Also, if we would do programming in MP, I would more tend to in-system programming, but that  must be discussed with my colleagues first.

Regards

Guenter

Further question: Is Enable Delay as described in datasheet (SWCS128A) section 5.6.3 user configurable through I2C (didn't find appropriate Register bits) or is it also subject to factory OTP programming? With other words: Can I Change the 2ms or 4ms delay from BUCK1 to BUCK2/6 listed in Figure 5-9?

If these delays are factory OTP, how are the settings for both, the 650860 and the 6508640?

regards
Guenter

Hi Guenter,

The sequencing of the voltage rails is all fixed in the OTP. The GPOs can be changed by I2C, but only in the volatile memory so they would need to be reset each time.

Are you working with Gunter Fettig? We have been discussing programming with him and determining best way to enable it. We have some of the collateral setup to enable this and can work with you 1-on-1 via email to figure out how best to enable for debug purposes and possibly in-line. 

The delays used can be found in the sequence diagram. There will be 1-3 per OTP, depending on how complicated the sequence is. The TPS650860 power up sequence can be seen in Figure 5-9 and was designed to showcase the types of sequencing the part can do. Namely, delay from a fixed CTL signal, immediate sequencing from previous rail PG, or a combination of both. Timing options are 2, 4, 8, 16, 24, 32, and 64 ms and set independently for power up (delay after all PG / CTL requirements are met) and power down (after any of PG / CTL requirements are lost - i.e. the assigned CTL pin falling).

Find attached the most recent version of the TPS6508640 sequence I worked on. It may not be 100% up to date but it should be 95% correct at least.TPS6508640_Sequence_and_Voltages.pdf

Hi Kevin,

Thanks for your answer. This confirms my guesses.

Yes, we are in contact with Guenter Fettig and had a meeting yesterday. Let's further communicate through him.

Regards

Guenter