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BQ76940: REGSRC fet gate - V10X or V5X

Ran Aloni
Expert 2386 points
Other Parts Discussed in Thread: BQ76200

Dear All,

some concerns about REGSRC circuitry:

1) EVM allows a selection between connecting the REGSRC fet gate to V5X or V10X.
can you supply a "thumb rule" on when it is best to use either?

if I understand correctly, you would use the V10X when you don't have enough cells on each sub-component, to have the FET on, on lowest possible cell voltage.

2) 5 cells of Li Ion can potentially create Vgs = 21V, which can damage the FET. what can be done?

3) in a 14S I'm using, the highest voltage can be 58.8V. absolute max of the pin is 36V. is there extra circuitry inside the chip to handle this voltage?
should I connect the DRAIN to V10?

Thanks, Ran

  • 0
    TI__Expert 6085 points
    1) Rule of thumb would be, during the a heavy load or short circuit event, the REGSRC should provide enough drive to maintain the drive outputs of REGSRC to provide headroom for Vgs of the FET.
    REGSRC drives the FET, typical input range of 6-25V; For FET performance a higher voltage is good. for low Power dissipation lower voltage of the REGSRC is desired. a constant supply of of 13V-15V. VC5X and VC10X are heavily filtered references. But you may pick other another cell to provide as gate reference to the source follower FET over the Dynamic range of the BAT. In general,
    2) scale the voltage of the Vgate with a series Rgate. On the drain side of the source follower, add R(drain) and add R_source; also add a series diode with ( small Vf)to prevent the FET from ESD on the PACK +.. Add a resistor across the diode.
    3) The Drian should connect via R(drain) resistor to the top BAT STACK.
    thanks
    vish
  • 0 in reply to Vish Nadarajah
    Expert 2386 points

    Dear Vish,

    is this what you mean?

    I don't know what will be the typical Id of the transistor, so I cannot imagine the Ig and the voltage on R54 and R59.

    but I believe it should be enough for a short circuit spike and a ESD spike as well.

    I must add that I will not use the REGSRC to drive the FETs, I will use BQ76200 charge pump driver.

    should I replace the BST82,215 to a FET with +-25V absolute Vgs values?

    regards, Ran

  • 0 in reply to Ran Aloni
    Expert 2386 points

    adding the picture that was missing from last post.

  • 0 in reply to Ran Aloni
    TI__Expert 6085 points

    yes, you can have the diode/resistor configuration on the drain of the FET. That will suppress the excursions of the VBAT. The configurations drawn, will prevent

    the drooping of the REGSRC when BAT is drooping and heavy loads.

  • 0 in reply to Vish Nadarajah
    Expert 2386 points
    Hi,
    just noticed, in my schematics drawing, R54 should be 100K according to EVM.
    is this to limit gate current?
  • 0 in reply to Ran Aloni
    TI__Expert 6085 points
    yes, the Rg (in series to the gate of the FET). Typically referred as Drive current which can be varied to control the slew rate of the FET an Tr/Tf by controlling the gate current.