TPS65177 code(Register Setting) checksum

Kevin Wen

Other Parts Discussed in Thread: TPS65177

Hi team,

would you please help to provide the checksum of below code (register setting) of TPS65177? thanks.

AVDD	HVS OFS	C-LIM	V IO	V CORE	HAVDD	HVS OFS	VGH-L	VGH OFS	GPM	VGL	Channel disable	Soft-start
1	2	3	5	6	7	C	8	9	A	B	0	4
29	5	0	B	6	1F	0	A	4	3	4	0	0

Kevin

AVDD HVS OFS C-LIM V IO V CORE HAVDD HVS OFS VGH-L VGH OFS GPM VGL Channel disable Soft-start

1 2 3 5 6 7 C 8 9 A B 0 4

29 5 0 B 6 1F 0 A 4 3 4 0 0

over 9 years ago

0 Ilona over 9 years ago

TI__Expert 8010 points

Hello Kevin,

I need to double check with the designer about the checksum.
I have one question to better understand the request:
After each data transmission (byte) the receiver has to set the acknowledge bit. Why do they not use this acknowledge bit? They can set a counter to sum up all acknowledge bits set.

Thank you.
Best REgards,
Ilona

0 Ilona over 9 years ago in reply to Ilona

TI__Expert 8010 points

Hello Kevin,

For the given register setting (configuration file saved from GUI) the checksum using the CRC23 algorithm is:

DEC: 2833529845, HEX: A8E43BF5

For your reference I have used an open-source checksum calculator that is available here: www.checksumcalculator.com

Best Regards,

Ilona

Fullscreen TPS65177_sample_register.txt Download

AVDD	HVS OFS	C-LIM	V IO	V CORE	HAVDD	HVS OFS	VGH-L	VGH OFS	GPM	VGL	Channel disable	Soft-start
1	2	3	5	6	7	C	8	9	A	B	0	4
29	5	0	B	6	1F	0	A	4	3	4	0	0

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TPS65177 code(Register Setting) checksum