LM27402-based design's output oscillates when the load reaches a certain point (not sure were that is exactly, but is in excess of 4A). Vin = 12V, Vout = 1V, Iout_max = 9A, switching frequency is 756 kHz (from external sync). Oscillations have a pk-pk voltage of about 125 mV and a frequency of around 22 kHz.
Output capacitance is 60 uF, implements with six 10 uF caps in parallel (estimating ESR to be 0.5 mohm), and the output inductor is 600nH (DCR 4.1 mohm). Using the LM27402 design calculator, the LC Complex pole location is 27 kHz, Q = 1.1, and the ESR zero is about 5.3 MHz. Compensation loop component were selected to roughly match these values, but resulted in the instability seen.
Varying the component value of Rc1 in the compensation loop corrects the problem mostly, as some damped ringing on load transients are still seen, but much reduced (max pk-pk of 30 mV). Fz1 is now at 10.6kHz, Fz2 at 28.3 kHz).
I suspect that the actual value of the output capacitor is not at my target, so the compensation loop response is not being tuned correctly. I'm in the process of re-selecting parts, but I have some questions:
The design calculator specifies a maximum ESR for the output cap, but is there a minimum that should be observed? Does having the ESR pole placed too far out have a detrimental effect from having the feedback loop bandwidth too wide? In general, is it a bad idea to use caps in parallel?
An example design in the datasheet shows a diode in parallel with the low-side FET, but there is no mention of this option in the design guide section, nor have I found any other reference to a diode in that part of the design. Under what conditions is it advisable to have this diode in the design?
Thanks!
