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UCC28704

yaylaci
Prodigy 40 points
Other Parts Discussed in Thread: UCC28704

Hi all,

I am interested in your UCC 28704 product. But I have some concerns:

-I  have made some simulation with ORCAD and even if i change unimportant things like  ( input power source) it shows different results. What is the reason?

-In order to accelarate simulation time i increase step size 20 ns to 100 ns and according to control theory it should not create proeblem because of IC max switching frequency is 85 kHz. But again it shows different results.

And lastly from evaluation model UCC28704 uses  a transformer from Wurth Elektronik with a part number of 750315841. But i think it is a custom product and it is not at Wurth Elektronik catalog. Therefore do you have any COTS transformer suggestion for UCC28704.

Thank you very much for your time and considerations.

Regards 

Yaylaci

  • 0
    TI__Expert 4015 points
    Hi Yaylaci, a few points.
    I don't know how your simulation is set up, or even what you are simulating. From what you've said I'm guessing it's loop response, but changing the input voltage in a flyback (assuming your using a flyback) changes the duty cycle and therefore affects the loop gain.

    Again depending on the specifics of the simulation, changing the step size may affect the duty cycle and frequency somewhat, this may affect the result.

    I will enquire about a transformer drawing for the UCC28704.

    Thanks
    Billy
  • 0 in reply to Billy Long
    Prodigy 40 points
    Thank you very much Billy for your answer.

    I have done only example model under www.ti.com/.../toolssoftware. even if I change source type (not amplitude) it gives different results...

    As you said from the loop response can be affected from step size but from block diagram I can not see internal control structure frequency but from control theory i can said that if the Ic switching frequency is 100 kHz than control part has a 1 MHz and the for simulation 10 MHz (100 nsec) should be enough. But the model has 20 nsec time step and even if the step size changed to 40 nsec again it shows different results.

    for example from the model from the link has some initial conditions on output capacitors, even if i change the values sometimes it shows different results.

    Thank you very much again.
  • 0
    TI__Mastermind 30441 points

    Hello Yaylaci,

    Inside the model there are many latches and flops that require step size of  at least 20n . Using 100ns will defienetly causes the internal circuitry to miss all clk edges and  give you wrong results. If you want to speed up the simulation time, I suggest to add initial conditions at the output node and cap ( unless you want to see the start up behavior from 0 volt). I hope it helps you to resolve the problem.

    Kind Regards,

    Arash