Is there an internal testing procedure for checking the proper PCB-connection of the chip without setting up all the rest of the resistors and capacitors? For QFN-housing with pads only below the chip it is for my understanding essential to check contacts.
By the way: May there be a mistake in the documentation: It says in chapter 7.3.2: "For the VBAT_UV feature to function properly, the system load should be connected to the VSTOR pin while the storage element should be connected to the VBAT pin." But shouldn't the system load be connected to V_out? Even in all your application examples, you never connected the system load to vstor. Actually, I am not really sure, what the externally accessible pin vstor should be good for.
Regards,
Volker