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UCC27211A - Application Question

Godjoker
Prodigy 40 points
Other Parts Discussed in Thread: UCC27211A-Q1, CSD19536KCS

Hello TI,
I got a circuit based on the Fig. 18 (Page 11 UCC27211A-Q1) (VDD: 12V HB bypaa capacitor 100 nF) . I want to switch 100V (as in Application Diagram) wit 6.7 kHz. The problem: As soon as the high-side FET is active the voltage on HS should increases to 100V but the UVLO (Undervoltage Lockout) disables the high-side driver (as written in chapter 8.3.2) when reaching VHB UVLO threshold. This produces a ringing of HO within the UVLO Hysteresis

Question is how to prevent this behavior?

I want a constant 100V rise/hold  on HS as long as HI (so should HO) is aktive.

Thank you very much for support!

  • 0
    TI__Intellectual 1880 points

    Hi Godjoker,

    Can you share some waveforms? Both what you observe and what you would like to see?

    If you apply VDD and let LI be high, it will let bootstrap capacitor to charge.

    Then, you can apply HI and 100V. 100V can be present all the time if it is acceptable in your system. You can control the switch node by HI.

    The  key is HI cannot be high all the time as bootstrap capacitor drains out after a while which turns HO off.

    As far as ringing is concerned, it is very difficult to eliminate any and all ringing effort.

    There are various ways to do so. One is optimum layout, second is reduce dv/dt by reducing drive current (by increasing gate resistor), third is by placing RCD snubber.

    Let me know if you need more information.

  • 0 in reply to Ritesh Oza
    Prodigy 40 points
    Hello TI,
    here are some waveforms:

    www.dropbox.com/.../AAA8D55zyqFHfnwdJ9VK3eMOa

    Channel A: HI (blue)
    Channel B: LI (red)
    Channel C: HB (green)
    Channel D HS (yellow)

    In picture setup you can see the schematic from the manual - instead of 100V we are switching 6V and 32V - but want to finnally switch 100V if erverything works as expected.
    In the picture "6V_Power" everything is as exspected.
    In the picture "32V-power" you can see that HS is increasing forcing VHB UVLO! As a result HI is deaktivatet/activated continuously.

    FETs used are CSD19536KCS, Gate resistors 0R. Layout is as close tho the recommended layout examample (page 19) as possible.

    As soon as the high-side FET is active the voltage on HS should increases to switing Voltage (i.e. 6V, 32 V , 100V) but the UVLO (Undervoltage Lockout) is active as soon as I want to switch voltages higher 6.7V. Do i need to increase HB voltage? - if so how? VDD is 12V?

    Thank You!