TPS3106K33 Output issue

PAN-M

Other Parts Discussed in Thread: TPS3106

Our customer is testing TPS3106K33.
When repeating on and off of the power, output is sometimes fixed at low.
Is there a regulation in time on from off of the power?

Regards,
PAN-M

over 9 years ago

0 Ryan Eslinger over 9 years ago

TI__Guru 55940 points

Hi Pan-m,

TPS3106 has two outputs. Do both outputs remain low? In order to help debug, could you provide a scope shot with Vdd, /RSTVDD, SENSE, and /RSTSENSE?

Very Respectfully,
Ryan

0 PAN-M over 9 years ago in reply to Ryan Eslinger

Mastermind 8375 points

TPS3106_reset_issue.pdfI attached customer's waveform.
Regards,
PAN-M

0 Ryan Eslinger over 9 years ago in reply to PAN-M

TI__Guru 55940 points

Hi Pan-m,

Thank you for the scope shots and schematic. We will attempt to replicate on the bench here.

Very Respectfully,

Ryan

0 Nicolás Román over 9 years ago in reply to Ryan Eslinger

TI__Intellectual 960 points

Hi PAN-M,

we were not able to replicate the issue shown on the scope-shots. Does it happen on regular terms?

It looks like the on off switching period is around 400ms. Is this correct?

Best regards,
Nicolás

0 PAN-M over 9 years ago in reply to Nicolás Román

Mastermind 8375 points

Hi Nicolas

This is their internal test.
They're investigating whether hangs by on/off of power or instantaneous power failure.
Please teach me necessary minimum time from off to on of the power.

Best Regards,
PAN-M

0 Mark Sellers over 9 years ago in reply to PAN-M

TI__Expert 6955 points

PAN-M,

We were unable to recreate your failure here in the lab. I have attached a waveform showing what we did here. Can you confirm with your customer that there is no high frequency noise on the power supplies that is causing this glitch?

Best Regards,

Mark

0 Nicolás Román over 9 years ago in reply to Mark Sellers

TI__Intellectual 960 points

Hi PAN-M,

I also did notice, that on the schematic the sense voltage is designed for 600mV and 620mV, witch is close to the threshold of this pin. Have you monitored this pin or tried to give it a little more room?

Best regards,
Nico

0 PAN-M over 9 years ago in reply to Nicolás Román

Mastermind 8375 points

Our customer measured attached waveform.
When VDD isn't dropped to 0V, It may reappear.

7178.Waveform.pdf

Regards,
PAN-M

0 Nicolás Román over 9 years ago in reply to PAN-M

TI__Intellectual 960 points

Hi PAN-M,

Thank you for sharing the scope shots. We are still not able to reproduce them, but there is one more think I'd like to ask you:

Is there a particular reason the customer has a cap at the /MR pin? I'm asking because we do recommend to leave it floating or tie it to VDD if it is not used. Other wise it can end up somewhere in between 0.3 x VDD and 0.7 x VDD and cause an undefined state.

I'm looking forward to here from you.

Regards,
Nicolás

0 PAN-M over 9 years ago in reply to Nicolás Román

Mastermind 8375 points

Nicolas

They don't use the function of /MR.
There is a capacitor of 0.1uF(to GND) by the drawing attached before.
" The input has an internal 100-kΩ pullup resistor, so it can be left open if it is unused."
It's written in the datasheet.

Is /MR better to tie to VDD directry?
Is it better to suggest an experiment to them?

Regards,
PAN-M

0 PAN-M over 9 years ago in reply to PAN-M

Mastermind 8375 points

Nicolas
Our customer said that this issue has disappeared when /MR is tied to VDD.
Pls. teach me this reason.
Does internal ligic fail by VDD undefined state?
Regards,
PAN-M

0 Nicolás Román over 9 years ago in reply to PAN-M

TI__Intellectual 960 points

Hi PAN-M,

Yes, on the pin description on page 3 of the datasheet we do recommend to leave the pin floating or tie it to VDD.

I personally would tie the /MR pin to VDD, since this would give you a defined voltage at the pin. If they already have a PCB build, floating the the pin, by removing the cap, will be the easier task.

Please let me know if the issue still occurs after performing one of the two steps mentioned above.

Best regards,
Nicolás

0 PAN-M over 9 years ago in reply to Nicolás Román

Mastermind 8375 points

Nicolas
They're eager to know a mechanism why did this phenomenon disappear?
When connecting /MR to VDD, VIH and VIL in /MR　become same.
Therefore an unsettled state of logic runs out.
Is it correct?
Regards,
PAN-M

0 Nicolás Román over 9 years ago in reply to PAN-M

TI__Intellectual 960 points

Hi PAN-M,

I guess that your customer put the cap there because of section 8.3.2. The paragraph witch mention the 0.1µF cap only applies if /MR is used.

If the cap is used as in the provided schematics, the /MR pin would keep the voltage of VDD up for a short time, even VDD was turned off. So technically you are exceeding abs max (/MRmax = VDD + 0.3V).

Best regards,
Nicolás

0 PAN-M over 9 years ago in reply to Nicolás Román

Mastermind 8375 points

Nicolas

Yes, my customer put the cap.
And also when having taken this cap, this problem disappears.
Our customer will finishe design with removing cap.

I appreciate your support.
PAN-M

0 Nicolás Román over 9 years ago in reply to PAN-M

TI__Intellectual 960 points

Hi PAN-M,

I'm glad I was able to help you.

Thank you for the feedback, it's always appreciated.

Best regards,
Nicolás

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TPS3106K33 Output issue