TPS562201 - Loop Gain

Please attach your measure result.

thanks!

Update.

DCAP2 has a normal LC double pole at 1/ (2*pi*sqrt(L*C)), so phase inverts from +180 degrees towards 0 degrees. The internal ripple injection forms a zero at a higher frequency, so phase rises back towards 90 degrees at high frequencies. Since phase never goes to zero except due to sampling effects, the concept of gain margin is not applicable. The phase in your measurement is rising higher. Do you have only ceramic capacitors on your output?

Hi John,

Because output voltage have some noise, I has add 100uF electrolytic capacitor on the output side.

It will reduce output rippel noise.

Does this have any side effect??

Dear Tucker

Looking forward your reply

Thanks

You have to be careful about adding electrolytic capacitors to the output. It will have an ESR zero that may affect the loop response. If you have HF noise a small value ceramic such as 0.1 or 0.01 uF may be more effective. You could also consider an RC snubber from SW to GND.

Dear John,
Thank you for your reply.

I has try RC sunbber in SW pin to GND. It can't reduce output noise.

Does this have any problem for my loop gain curve?? (100uF-E cap)

Is Phase margin rising higher?? Do you have any suggest and reduce it??

can i see a waveform of your output noise? Please include the SW node. Without knowing the ESR of your added capacitor it is difficult to estimate the loop change.