Hi Team,
Considering using LM5022 in a Flyback design, Vin 6-36V, Vout 15V @ 3A.
Can we expect trouble if we try and generate RT/SYNC in an FPGA powered by the PSU’s next stage +3V3 buck. We’ll make the FPGA tristate until its power and configure is good, and we can stop it gracefully after a falling clock edge when we power down. Basically clocking and transition over between RT/fixed resistor and FPGA sync during FPGA power up/down.
Light load operation and if there is a mini load requirement for LM5022 to perform.
Any tips on compensation loop design if needed to switch between CCM and DCM.
Magnetics tips/recommendation for high switching operation close to 1Mhz.
Thanks,
Jani
