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TPS767D301 resistance value between the 1GND and 2GND internal to the IC

Kishen Someshwar
Intellectual 1625 points
Other Parts Discussed in Thread: TPS767

Hello Team,

I have a customer who is using the TPS767D301 to design their products. The issue they are facing is documented below:

" We've got a HW failure where the TPS767D301 1GND is tied to a digital return that is open back to the power supply return and the 2GND is tied to an analog ground which is tied back to the digital power supply on a harness.  Here's a sketch ( Attached )

Neglecting the harnessing loss, the voltage the TPS767D301 reset circuit sees will depend on the resistance between 1GND and 2GND internal to the TPS767D301. hence the reason for my question.  Is there a resistance value between the 1GND and 2GND internal to the IC and what would the current carrying capability between those two grounds be (the max current that could be accommodated internally flowing from 1GND to 2GND,  Referring to the diagram, that would be the sum of the load currents returning from the loads being supplied by the 1IN and 2IN inputs and returning on 2GND only (since the 1GND wire is broken in the harness back to the source power supply)? "

From the datasheet, I do not see any indication whether there is any resistance value between the GND1 and GND2.


I appreciate your time and attention towards this issue.


Thanks

Kishen

DOC20160920182111-863.pdf

  • 0
    TI__Guru 55940 points
    Hi Kishen,

    The two ground pins are not directly connected within TPS767. 1GND is the ground reference for LDO1 and 2GND is the ground reference for LDO2. As such all pins and external components for LDO1 should be connected to 1GND. All of the pins and external components for LDO2 should be connected to 2GND.

    Very Respectfully,

    Ryan
  • 0 in reply to Ryan Eslinger
    TI__Intellectual 1625 points

    Hello Ryan,

    Thank you for your attention towards this post.

    I previously referred another post  ( attached below) where it was said that "The GND pins are also connected inside the IC but should also be tied together at a central point on the board as well."  

    Am I interpreting this statement wrong?


    I appreciate your support on this.


    Sincerely,

    Kishen



  • 0 in reply to Kishen Someshwar
    TI__Guru 55940 points

    Hi Kishen,

    Yes the two grounds are technically connected through the exposed pad at the bottom of the package; however, this connection is not adequate to be used as the ground reference point.  The individual ground pins must still be connected to be used as the reference for the LDO (1GND for LDO1, 2GND for LDO2).  This is the reason Scott mentions : 

    "The GND pins are also connected inside the IC but should also be tied together at a central point on the board as well."

    Very Respectfully,

    Ryan

  • 0 in reply to Ryan Eslinger
    TI__Intellectual 1625 points
    Hi Ryan,

    I understood the point. Thank you very much for your support on this. It is appreciated.

    Kishen