Hi team,
My customer is evaluating TPS62560 on a prototype.
When he was evaluating it,the TPS62560 destruction occurred.
When he checked the destroyed IC(TPS62560),the resistance value between the SW pin
and GND was 20Ω.
*We already sent the destroyed IC to TI to analyze it.(curve tracer etc..)
I attached the customer's circuit diagram and the result which my customer evaluated
a other circuit board(same prototype) as follows.
*However the TPS62560 on that circuit board has not been destroyed yet.
I wonder if you could answer my two questions.
In addition,if you have any advices,please let me know.
Q1) When the approximately 7.4V voltage is applied to the SW pin
during several nano seconds at the TPS62560 starting up,
is it thought that the above phenomenon leads to destruction like this time?
*cf. attached file TPS62560_circuit.xlsx "Resut of evaluation"
Q2) I attached the result that I simulated the TPS62560 circuit using TINA-TI as follows.
From the simulation result,the low side FET turns on during approximately 25us
before the switching operation, and the large current flows.
＊cf. attached file TPS62560_TINA.xlsx "simulation results"
I think that the low side FET will be destroyed,if that phenomenon occurs.
Though we have not observed the phenomenon that the low side FET turns on
during 2-30 microseconds on the actual circuit board,is there possibility that
the above phenomenon occurs on the actual circuit board?
Best regards.
Tsuyoshi Tokumoto
