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UCC28C43 internal series diodes

Hiroshi Doi35
Expert 2845 points
Other Parts Discussed in Thread: UCC28C43, TL431

Hi All,

My customer failed their final trial. And mass production delayed.

They use a lot of UCC28C43 in parallel.

FB is connected to GND.

When COMP voltage down to 1.3V  each UCC28C43  (COMP is connected by use PNP transistor such like Fig. 25 soft start),

some of UCC28C43 output pulse are disappeared  and gatherd output become fail.

They checked PNP Tr and changed but no change.

They changed UCC28C43 and the problem found UCC28C43 internal series diodes valuation.

They asked me,

Typical Vf of two series internal diode. And their tolerance.

If someone have good idea to avoid this fail, please teach me.  IC cahnge is OK.

Thank you,

H.DOI

  • 0
    TI__Guru**** 191445 points
    Why would you tie VFB to GND? Can you post your application schematic?
  • 0 in reply to JohnTucker
    Expert 2845 points
    I'm sorry I can't answer. Japanese Major Elec. company never open their cct.
    If each output of UCC28C43 regulated and return to each VFB, is this problem resolved?

    H.DOI
  • 0 in reply to Hiroshi Doi35
    TI__Genius 9130 points
    Doi-san

    It sounds like the customer is shorting FB to GND and then explicitly using an external error-amp or feedback regulation mechanism to control the COMP level on all IC's in parallel to be the same voltage level, by pulling current out of the COMP pins. Is that correct? As John said, it would be helpful to post a schematic, but understand if you can't.

    GNDing FB and connecting the opto to pull down directly on COMP is a very common configuration used in isolated converters where the error amp (TL431) sits on the isolated secondary, and demand is coupled to primary through an opto.

    If this is the case, the individual UCC28C43 IC's will not all have exactly the same peak current and on-time, despite the same COMP level - this will be due to mismantch in the COMP to CS offset (the 2 series diodes you refer to), and also mismatch in the COMP to CS gain.

    As COMP level is reduced, the IC's with higher COMP to CS offset will hit zero duty cycle first, which seems to be what you are seeing?

    The COMP to CS offset max/min is not specified for UCC28C43, and I don't think it's published for any of the 284x type IC families.


    When you say several IC's are in parallel, what are the individual drive OUT pins controlling?

    If we get more info about the application, the requirements and the level of matching performance required, we can comment further and possibly make recommendations to improve the design.

    Thanks
    Bernard