Hi,
What kind of OVP feature do we have for TPS65094x power rails (buck and LDO)? What is the OVP threshold for them in datasheet?
Thanks!
Antony
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Hi,
What kind of OVP feature do we have for TPS65094x power rails (buck and LDO)? What is the OVP threshold for them in datasheet?
Thanks!
Antony
Hi Kevin,
Will OCP cause PWR FAULT as OVP did that you describe above? Or it's just related to OCP bit in OFFONSRC register? Please share OCP related information with me here.
Thanks!
Antony
Hi Antony,
OCP does not inherently trigger a power fault, but will likely cause one. As OCP kicks in, the output current provided by the buck will start to droop and as a result the Vout should start to droop as well, resulting in an PWR FAULT due to undervoltage.
There is a point where OCP will start to trigger and the output will start to droop, but stay within the 8% and not trigger power fault. It's only about 100 mA in width though, so in nearly all cases the OCP will result in undervoltage which results in PWR FAULT.
One important note is that the OCP bit in the OFFONSRC register actually triggers for any PWR FAULT, both undervoltage and overvoltage, so it does not actually necessarily mean an OCP event has happened.
If customer wants to confirm an actual OCP occurred, there is another register they can read:
Hi Antony,
They can scope RSMRSTB to see it go low. That said, OCP is not intended to overpower a large power supply. I broke my board trying to test this further today.
Hi Antony,
I realized today there may be a fundamental difference in what I am describing as overvoltage protection and what customer may be looking for. I was referencing our PMIC's ability to shutdown in case it starts to regulate high. If they are looking for protection from an external overvoltage source, then they would need separate circuitry.
The PMIC OVP is intended to shut down the BUCK if it starts regulating outside of the target window. It is difficult to test since the BUCK will do everything in its power to ensure this doesn't happen, especially in DCAP2 architecture.
One option to test on the EVM is to use VCCGI to overpower VNN. Start by shorting VNN and VCCGI with PMIC off. Turn on PMIC by setting CTL2 high (THERMTRIPB), then CTL1 (PMICEN), then CTL5 (SLP_S4B), then CTL4 (SLP_S3B), then CTL3 (SLP_S0B). At this point VNN should be on, VCCGI still off. Set VCCGI to 1.3V by I2C. VCCGI should be able to overpower VNN since OCP for VCCGI > OCP for VNN. At the point that VNN passes the power good threshold for 30 us, the PMIC will shutdown both VNN and VCCGI and reboot with VCCGI off again (default state is OFF until SoC passes I2C VID). It should look like:
The top signal is VNN, the bottom is RSMRSTB. I short a BUCK1 and BUCK2 together and then set BUCK2 to 1.3V and we see BUCK1 power fault. I actually did the testing with a TPS650842EVM-116 but results should be approx the same for a TPS65094x part as well. PMIC tries to restart 10 ms after power fault since I have PMICEN tied high and continues power faulting until the voltage discharges just off screen and boots properly.
Note: they will need to investigate on their board if this test is possible without breaking their system.
Hi Kevin,
Customer try two different way to create OVP as below.
Case1: Use a power cable with 1.6V from power supply to touch VNN output shortly.
Case2: With a wire from VCCGI/BUCK2/1.3V to touch VNN output shortly.
The reason why they just short the VNN output to some higher voltage shortly is to simulate their testing standard. We can see RSMRSTB become low shortly and back to high level. Does it mean PMIC shut down shortly due to OVP and reboot because OVP condition not exist anymore? Customer expect PMIC would just shut down and not reboot. But this is not our PMIC bahavior, right?
Please check below scope shot from customer for these two cases mentioned above and let us know if the behavior is correct or not. Thanks!
CH1:VNN(BUCK1) CH2:VCCGI(BUCK2) CH3:RSMTSTB
Case1_1:
Case1_2:
Case 1_3:
Case2_1:
Case2_2:
Antony
Hi Antony,
All of the plots appear to match expectation. The PMIC shuts down and after shutdown it checks the state of the control pins to know what to do next. You are correct, it does not stay off. A microprocessor is typically used to decide whether to stay off or try to power on again.