I am trying to piece together a squeeze routine to verify when a sense line is not connected to the battery stack. We are using a single bq76PL455A-Q1 on a 6S pack which has been working quite nicely. My questions are below.
1.) Do I use OV/UV window comp circuits or the AFE to detect the increased voltage on the N+1, N-1 lines when squeezing on sense line N?
My confusion is the from section 7.3.12.8.1 Window Comparator Special Considerations of the data sheet which states ´ “Only the comparators can see the increased voltage not the AFE” the but the “Safety Manual for bq76PL455A-Q1” states, under Section A.6 “BatBroken” that “All odd channels should be squeezed and all channels sampled. Then all even channels should be squeezed and all channels sampled.
Please clarify.
2. ) What is the proper setup for squeezing? Currently, I have the following commands
//clear all faults
nSent = WriteReg(0, STATUS, 0x38, 1, FRMWRT_ALL_NR); // clear fault flags in the system status register
DELAY_US(1000);
//set the squeeze reisitor enable bit
nSent = WriteReg(0, TSTCONFIG, EQ_SQUEEZE_EN, 2, FRMWRT_SGL_R);
DELAY_US(1000);
// Verify that the register was written to
nRead = ReadReg(0, TSTCONFIG, &bTemp, 2, &SciB_status);
DELAY_US(1000);
//Set the balance continue bit when a fault occurs.
nSent = WriteReg(0, CBCONFIG, BAL_CONTINUE, 1, FRMWRT_SGL_R);
DELAY_US(1000);
// Verify that the register was written to
nRead = ReadReg(0, CBCONFIG, &bTemp, 1, &SciB_status);
DELAY_US(1000);
// Set up squeeze resistors.
nSent = WriteReg(0, CBENBL, SQUEEZE_EVEN_CH, 2, FRMWRT_SGL_R);
DELAY_US(1000);
//verify squeeze channels were set.
nRead = ReadReg(0, CBENBL, &bTemp, 2, &SciB_status);
DELAY_US(2000); // Requires 2 ms settling time.
Am I missing anything? Any help in this matter would be greatly appreciated.
Best regards,
Matt