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Startup problem with TPS650832

Dennis Keats
Prodigy 70 points
Other Parts Discussed in Thread: TPS650832

I am using a TPS650832 with a Skylake-H processor. The 3.3V rail is coming up as expected, followed 11 msec later by DPWROK being asserted. After 60 usec DPWROK is being deasserted. Reading the internal registers I find that the VRFAULT bit is set (bit 4, reg 0x08) and that the V085A_FAULT bit is set (bit 0, reg 0x17). I don't understand why this fault should be detected as only the 3.3V (VR3)  and 1.8V (VR2) power supplies have been enabled at this point (ENVR3 from 3VLDO, ENVR2 from DPWROK).

  • 0
    TI__Genius 16870 points

    HI Dennis,

    It looks like somehow your V0.85A rail is being enabled but, the power good is not set.

    On the TPS650832 the V0.85A rail is monitored by VSC. VSC is looking for a logic signal input, High or Low. The PMIC knows to look for this signal once ENC goes High so, from your readout I think you are having the following issue:
    ENC goes HIGH and VSC is not receiving the power good from the external regulator that is meant to be used with the TPS650832.

    Check the ENC signal with the VSC signal on a oscilloscope. See if the ENC goes high before the VSC does. It is ok if ENC goes high before VSC but, the PMIC times out at 10ms determining there is a fault on V0.85A. So, if ENC goes high before VSC by more than 10ms then that is a problem.

  • 0 in reply to Michael Green
    TI__Genius 16870 points
    Note to all users that received the above reply via email: I revised the post to change all mentioning of VSD to VSC and END to ENC. It was a typo and is now correct as seen above.
  • 0 in reply to Michael Green
    Prodigy 70 points

    Problem fixed by changing the VSC input to match the enable.