Hello Team,
I am ethan Kim from TIK and support Mass market as FAE.
I got a customer request for reviewing B/D review.
Could you please refer to attached and give me the feedback?
From LCD datasheet page 7, LCD require the sequence below. DVDD →over 10ms → AVDD → VGH/VHL : LCD_DATASHEET.
So customer did change
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C24 22pF -> 4.7nF to delay AVDD.
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For VGL, VGH timing delay, C35/C36 0.01uF -> 0.47uF.
So question is
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Is it okay to change cap like thos value?
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For VGL, VGH timing delay, what I know is DLY1,2 pin makes the dealy of VGL,VGH. But we change C24 for VDD delay. Is it correct for LCD spec?
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Could you give me some feedback for PPT schematic?
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Is there any other way to change AVDD delay?
Regards,