This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

tps65150 urgent question about sequnce

Hello Team,

 

I am ethan Kim from TIK and support Mass market as FAE.

I  got a customer request for reviewing B/D review.

Could you please refer to attached and give me the feedback?

 

 

From LCD datasheet page 7, LCD require the sequence below. DVDD →over 10ms →  AVDD → VGH/VHL : LCD_DATASHEET.

So customer did change

  1. C24 22pF -> 4.7nF to delay AVDD.

  2. For VGL, VGH timing delay, C35/C36 0.01uF -> 0.47uF.

 

So question is

  1. Is it okay to change cap like thos value?

  2. For VGL, VGH timing delay, what I know is DLY1,2 pin makes the dealy of VGL,VGH. But we change C24 for VDD delay. Is it correct for LCD spec?

  3. Could you give me some feedback for PPT schematic?

  4. Is there any other way to change AVDD delay?

 

 

Regards,

 

 

 

  • Hello Ethan,

    1) Delay of AVDD (10 ms after VI)

    I do not recommend the current capacitor change. C24 is the feedforward capacitor of the boost converter and as this it is affecting the loop characteristic, it has only the goal to optimize the transient response. If the feedforward cap is to large, it can cause the loop gain to crossover too high in frequency and can result in instability. As the chosen capacitance is almost 500x times higher than recommended it is very likely that the converter will not work stable. did you already evaluate the current schematic? I recommend to do a stability check (load transient) to see if the converter works as expected. For deeper information about feedforward network and stability measurements please refer to:

    For reliable delay of AVDD I recommend to use the isolation switch as described in figure 26 and additionally add a RC filter to delay the turn-on of Q1.

    2) Delay of VGH/VGL

    In general I do not see a problem with changing the delay capacitance at this value. Please verify that this is working reliable in the system.

    3) Schematic Review

    The output capacitor of the AVDD rail is rated too low. The actual capacitance at an applied voltage of 10.8 V of a 6.3 V-rated capacitor would nearly be zero.

    Please choose capacitors that are roughly rated double the applied voltage and have an effective capacitance of 10 uF .
    For the AVDD rail I recommend to use a 22uF/16 V with a size of 1206, please refer to chapter 8.2.2.4 for capacitor selection.

    Thank you.

    Best Regards.

    Ilona