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LP5907 - high impedance outputs?

adomino
Intellectual 1000 points
Other Parts Discussed in Thread: LMK61E2, LP5907

Hi guys,

I have a question regarding the LP5907 on the LMK61e2 EVM. If I want to power the OSC device via external power (as opposed to usb), but I don’t have an sma connector for power, can I leave J2 floating to disable the LP5907 LDO and apply 3.3V to VDD_REG?

Basically I am wondering if there would be an issue applying 3.3V to Vout of the LDO when the LDO is powered down. Looking at the DS for the LP5907, if enable (EN) is low and the LDO is fully disabled, automatic output discharge is activated. So we have a 230Ohm pull down giving us a fairly low impedance path to ground. So I am thinking VDD_Reg cannot be used as an external input to power LMK61e2. Let me know if this is correct. 

  • 0
    TI__Mastermind 22610 points

    "... if there would be an issue applying 3.3V to Vout of the LDO when the LDO is powered down..."

    You will be in violation of the Vout Absolute Maximum Ratings by having Vout > Vin, but IF the input is open (J2 open) the likelihood of damage is minimal.

    With 3.3V applied to VDD_REG (LP5907 VOUT) the LP5907 Cin capacitor (C10, 1uF) will first charge through the internal PMOS body diode to about 2.9V, and the EN pin will eventually charge through the RC delay circuit (R6 33k, and C12 0.1uF). When the C12 charges to about 1V the EN pin crosses the 'ON' threshold and the auto discharge circuit should disable. During power-on there will be a window of time where Vin is above the minimum operating voltage and Ven is still below the 'ON' threshold (C12 still charging) such that the auto discharge circuit will be enabled. There will still be reverse-current going into the OUT pin, to the IN pin, but that will be in the order of micro-amps.