Thermal issue of TPS659037

Hello Michi,

To reduce the PMIC temperature, there are a couple of options:

1. Lower LDO input voltage where possible.  If there are any 5V input LDOs with 1.8V output, you could consider lowering the LDO input to 3.3V.
2. Add a heat spreader or heat sink.  This won't reduce power consumption, but will lower the junction temperature of the PMIC.
3. Lower the processor power consumption when temperature is getting hot.  This can be done by reducing frequency or utilization, but also lowers processor performance.  This might not be acceptable, but want to provide it as an option in case it can be done.

We also have a power estimation tool, if you want to see how any voltage or current changes would affect the expected junction temperature.

e2e.ti.com/.../3366.power-estimator-tool

Regards,
Karl

Hi Michi,

I wanted to give a couple additional points to consider.

1. Lower SMPS switching frequency will have higher efficiency, since this reduces the switching losses of the converters.  Although the internal clock cannot be changed, it is possible to use an external clock to synchronize to a lower frequency than 2.2MHz.
2. Having a large GND pour on top and bottom layers can also help with heat dissipation.

Regards,
Karl

Dear　Karl-san,

Thank you for your quick reply.

PMIC's power estimation tool is very helpful, I think. I will submit it to my customer.

Regarding your advice in your first reply, I will comment as the below.

1. According to my understanding, my customer's PMIC connection is the same as Figure 1. Processor Connection With TPS6590376ZWSR in SLIU011C document. So customer use 3.3V for 1.8Voutput LDO.

2. Of course customer use heat sink.

3. Customer is considering to reduce processor freuqency from 1GHz to 600 MHz.

Regarding to your 2nd reply, I need your help for my understanding.

1. Lower SMPS switching frequency will have higher efficiency, since this reduces the switching losses of the converters.  Although the internal clock cannot be changed, it is possible to use an external clock to synchronize to a lower frequency than 2.2MHz.
2. Having a large GND pour on top and bottom layers can also help with heat dissipation.

Regarding #1, switching frequency,  is the minimum frequency 1.7MHz(from TPS659037 4.11 DC-DC Clock Sync Characteristics)? Also, for using external clock,  is there any schematic changing needed, except for adding clock input? 

And this is important,  how efficiency improvement is expected by this modification?

Regarding #2, what is the meaning "Having a large GND pour on top and bottom layers"? Is it to make bigger  GND plane?

Please advise me again.

I appreciate your quick reply.

Best regards,

Michi 

Hello Michi,

>Regarding #1, switching frequency,  is the minimum frequency 1.7MHz(from TPS659037 4.11 DC-DC Clock Sync Characteristics)? Also, for using external clock,  is there any schematic changing needed, except for adding clock input?

[Karl] Yes, 1.7MHz is the minimum switching frequency for the external clock.  And the only schematic change is to add the clock input, nothing else is required.

> And this is important,  how efficiency improvement is expected by this modification?

[Karl] One of the sources of losses in a buck converter is switching losses.  Every time the converter switches from high-side-on to low-side-on (or the opposite), there is some power loss.  The application note Power Loss Calculation with Common Source Inductance Consideration for Synchronous Buck Converters Section 3 explains this in more detail.

Because there is power loss at every switching cycle, this means if we reduce the number of times the MOSFETs switch, we can reduce the losses from the switching.  So by running at 1.7MHz, the FETs switch 1,700,000 times per second, and at 2.2MHz they switch 2,200,000 times per second.  Therefore the switching losses are higher at 2.2MHz, assuming all other things are equal.

The total improvement will depend on output voltage, load current, and other factors, but typically for non-zero load we see between 1% and 2% improvement from 2.2MHz to 1.7MHz.  This means 80%->82%, or 90%->91%.

> Regarding #2, what is the meaning "Having a large GND pour on top and bottom layers"? Is it to make bigger  GND plane?

[Karl] Yes, I mean that you should have a large GND area on the top and bottom layers.  The GND copper acts like a metal heat spreader, and typically GND is poured over the whole top and bottom layers where there are no other traces.  So if possible, your customer could try to increase the GND area connected to the PMIC.

Regards,
Karl