TPS549A20 - Capacitance on PMBus pins..

Amanda Ross95

Other Parts Discussed in Thread: TPS549A20

Hello there,

I'm curious to understand what maximum capacitance each of the following pins can sustain without interfering with normal operation?

N_ALERT
SCL
SDA

Also, just to make sure, please confirm that pulling the 'EN' pin to the 'VREG' pin will not work as an enabling mechanism for this device. This question has been raised to me but I have not seen it done in any reference designs, nor is it called out as special functionality in the datasheet. I want to make sure I'm not incorrect before I confirm that it's not an option.

Thanks so much!

-Amanda

over 8 years ago

0 JohnTucker over 8 years ago

TI__Guru**** 191445 points

If this works like all the other DCAP devices, VREG is low if EN is low, so you cannot pull EN up to VREG to enable. I doubt that there is any capacitance specification for the PMBus control signals. You might look in the PMBus general specification. In any case the amount of capacitance on the control lines will affect the rise and fall times and may impair communications. You were not intending to introduce any intentional capacitance or are you just worried about parasitics?

0 Amanda Ross95 over 8 years ago in reply to JohnTucker

TI__Intellectual 2740 points

Is there a recommeneded capacitance that should be placed near the PMBus pins? If so, what value?

0 JohnTucker over 8 years ago in reply to Amanda Ross95

TI__Guru**** 191445 points

I do not place any capacitance on PMBus pins when I design with PMBus devices. The TPS549A20 EVM does not have any capacitance on those pins either. The PMBus general specification should define the maximum allowable capacitance. You could look it up there. Why are you concerned about this?

0 JohnTucker over 8 years ago in reply to JohnTucker

TI__Guru**** 191445 points

I looked this up for you:

Max capacitance per bus segment (CBUS) = 400 pF
Max capacitance per DATA or CLK pin (CPIN) = 10 pF

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TPS549A20 - Capacitance on PMBus pins..