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UCC28051's error amp, howto build the behavior component ?

ericsson sunshine
Prodigy 250 points
Other Parts Discussed in Thread: UCC28051, PMP9730, TL431

Hi, crews :

May I ask a question about the error amp of UCC28051. 

Recently I was building a math model of UCC28051, so far I could build the schematic of PFC behavior by this UCC28051, and it works as expected.

But the final purpose is to utilize this UCC28051 to route a schematic of single stage PFC+flyback topology, under this step, I found the UCC28051 will always latch up caused by the "zero power detect" which is a feature of the UCC28051, that latch failure is voltage of pin.2 "COMP" is lower than 2.3V. I then found some reasons might cause this latch up issue happen, 

1). the feedback signal of "comp" (refer to PMP9730) came from bias winding of the transformer, the compensation is lagging.

2). the component of error amp built-in the UCC28051 was wrong, I simply use a current source which controlled by a different voltage to model the transconductance (typ : 90uS), but the question is is this enough ? Shall I view the error amplifier as a amplifier which normally treated as a gain of Vout/Vin, or as the datasheet said, a transconductance with 90uS ?

3). That's simply a compensation problem. Try continuing fine-tune the compensation paramters. (Already tried many times.)

About the 2). ,could someone give some suggestion , howto correctly build the error amp math model ?

Thank you very much

Best regards.

  • 0
    TI__Mastermind 31580 points
    Hi

    I have asked one of our applications engineers to respond to your post.

    Regards

    Peter
  • 0
    TI__Intellectual 1550 points

    Hi Ericsson Sunshine,

    To answer your questions above:

    1. I've looked at the reference, the FB signal is generated by the TL431 based compensation network and transmitted to the primary side through the optocoupler. Basically, the internal transconductance amplifier is bypassed. To get this function working, the Vo_sns pin has to be pulled below ENABLE as shown below.

    2. I think it would be too simplified if the transconductance amplifier is treated as an ideal voltage controlled current source. Modeling the accurate behavior of a power supply controller IC can take quite some time. For your information, TI may already have built a Pspice model for this chip which you can simply plug in to your system model to characterize the behavior of the chip. I couldn't find the Pspice model for this part on ti.com but I would suggest you reaching out to WEBENCH team within TI to see the availability of this model (https://e2e.ti.com/support/development_tools/webench_design_center/f/234).

    Regards,

    Wangxin

  • 0 in reply to Wangxin Huang
    Prodigy 250 points
    Hi, WangXin:

    Thank you.

    At the first, I thought the FB signal from the opto would discrete the switching PWM into discontinuous duration piece by piece, thus affect the line current away from sine wave (one reason of doing PFC). So that, I enable it (rather than tune the FB to about 2.5v*(301k+30.1k)/30.1k=27.5v, over the Vcc max rating) to about Vcc=16v. That's different from the reference.

    But I guess the sine wave current issue was solved by the heavy RC filter of driving opto+TL431.

    If you still trace this on, may I confirm the output short circuit failsafe condition of the reference design PMP9730 ? I predict the output voltage will decrease thus affect the Vdd (supply of the IC) decrease together, when lower than the UVLO, the IC will latch output. Thus feature the short circuit protection. (Since there is not much more detailed info about the PMP9730.)

    Thank you again, for the helpful answer.

    Have a good day.
  • 0 in reply to ericsson sunshine
    TI__Intellectual 1550 points
    Hi Ericsson Sunshine,

    I think your prediction could be verified with an output short test on the PMP9730.

    Regards,
    Wangxin
  • 0 in reply to Wangxin Huang
    Prodigy 250 points
    Hi, WangXin:

    Thank you for your suggestion, but I haven't got the PMP9730 demo board on hand.

    In fact, I do this for a pre-estimation of those single-stage PFC+flyback application, there is a scheme but not sure it will be put into practice. Due to the uncertain reasons I couldn't do much more effort about all this (resource wasting). But base on personal characteristic, I prefer preparing more materials which might be needed in the future, thus once if there is a rush plan from the boss thrown to me, the pressure of schedule would be much fewer, that could keep me from busy-bugging of my job and live more freely.

    Since it could possibly go into practice, I couldn't show more info about that design (models & schematic). Though the PMP9730 is sufficient enough.

    Thank you for the opinion.

    Best regards.