UCC28631 not starting up

USE RTF ... DUH  lol  

I had checked and rechecked the polarities and all are correct per the documents, and seem to be correct in the traces, unless i am misinterpreting them.  The numbers i used do not seem to make the spread sheet crab about it ... at least not for the UCC28631

R24, 66, Q7 are out of circuit -  i missed the fact that the start up current is virtually non existent so i will be forced to tap off before D12 for that power

VDD cycles from the 5V reset level to the 15V restart level though it is different depending on if the error reported is VDD UV or AC UV

the aux pin is "reading" 160V on the AC bulk capacitance and 80V peak on the secondary ... i might have to go back and check the diode and caps as well

there is a lot of pickup on the scope because i did not bother with clean connections.  called the supplier and the saturation current is close to 4A on the transformer design

ok ... in order i suppose  lol

i did try lifting the cap as i was suspect that our "stock" snubber was an issue, especially after reading some of the other forum threads, but to no avail.  was not concerned at all about the FET as it is avalanche rated

the extra load i did not think was significant since it should only be 5-10mA.  It is indeed for isolated rails for a power FET gate drive, a few comparators, and a couple isolators ... a second aux is out of the question do to creepage distances at medical isolation levels.  It is actually supplying +4V regulated to 3.3V for the logic, analog and boosted to the gate supply (convoluted but keeps down the current demand in standby), and -4V to improve the gate discharge rate.   If it turns out i do not need the -4V for discharge i can get rid of Q7, R66, D21, D22 and put a jumper in for C40 as those parts only make sure the forward mode results in a semi regulated negative rail.

While I can use different FETs in the application, I was hoping to have this portion of the board be a universal supply.  That said by my rough estimation the STB28N65, an inexpensive FET, has rise/fall times of 10nS yielding 1W of dynamic dissipation at 400V and 120KHz and around 1W static at 2A DC.  The D2 case is capable of dissipating 2W continuous with no heat sink, which was the logic behind that choice.  It looks like my space constraints might be loosened slightly allowing some on board heat sinking for additional reliability

as for the gate pull down, this was done a year ago and then was on hold.... i don't remember the logic for it. ... the preload is on the list of things to change already as well

I suspected the 107Ks could be lower, but the value was already in the design and the data sheet is vague on that.

It certainly would have been helpful to have the eval as a working starting point.  My transformer house says the leakage to the primary is 50uH of 550uH, but I am seeing over 100uH for some reason ... I have no data on the bias leakage, but using my lame equipment it looks like less than 1uH of the 8.6uH bias winding.

refusing to pose when i try to insert the xlsm file

Dan,

This E2E system may not like the xlsm file because of the macros - if you zip the file first, it should work ok.

When you removed the snubber, how did the waveforms change, if they did change? For sure, the Q5 Vds waveform (as viewed indirectly at the aux winding) does look strange, not how it should normally look. It rises quickly initially, then changes to a very slow rate of rise. And the first few cycles of DCM ringing also look strange as seen on the DRV & CS waveforms. Can you look at the Q5 Vds directly?

The transformer leakage inductance is very high – 50 uH out of 550 uH is probably already too much to be usable, but 100 uH sounds just way too high to work. Similarly, high leakage inductance on the aux winding will affect the VSENSE pin signal and the ability to correctly sense Vin & Vout.

I would suggest running at Vin < startup level (~113 V pk, 80 V rms) for initial debug, to make sure the switching waveforms all look correct. At say 100 V input, the HV pin will pull current to charge VDD, when Vdd hits 15 V the HV pin current source will turn off and the IC will attempt to start. It will generate 3 initial switching pulses on DRV at 15 kHz, and use these initial switching cycles to check for some non-zero signal at CS (to ensure that the CS pin is not shorted to GND), and to check the Vin & Vout levels via the VSENSE pin. The internal CS comparator will be set to the minimum demand level (~0.17-0.18 V). At 100 V input, theses 3 DRV pulses will be ~2.3 us duration (with 550 uH and Rcs = 0.4 ohm), with the CS ramping to ~0.17-0.18 V peak. During the DRV on-time, the VSENSE pin should swing positive to 9-10 V, and then drop close to zero during the off-time (Flyback interval) since Vout should be  close to zero, then when the secondary current decays to zero, the DCM ringing should be evident on all waveforms. Since Vin is to low, the IC will give up after these 3 initial DRV pulses, go to lower mode for 0.5 s (as VDD decays slowly), then discharge VDD to the 5-V reset level, and the cycle should repeat.

If Vin is held at this level, and if the main output is unloaded, the cycle of 3 pulses, shutdown and repeat will continue indefinitely, and after several seconds, Vout should be seen to be charging up slowly to a very low level, due to the small amount of energy being transferred during the 3 initial pulses. Eventually, Vout should settle at a low level where the output LED can be fwd-biased & R8 can discharge the output caps somewhat during the off-time.

You can then observe the waveforms during the 3 DRV pulses to make sure everything looks ok.

These are waveforms I took on another EVM, at input Vin = 100 V dc.

This shows VDD (pink) & DRV (green) during repeated restart attempts; each attempt is 3 DRV pulses, though that can't be seen at this timescale:

Zooming in to one of the restart attemopts, showing the 3 DRV pulses (green) with corresponding CS ramp (red) at the FET source, and the FET Vds (blue):

Zooming in further to one of these cycles, showing DRV (green), CS (red), VDS (blue) & aux winding (pink)

And same as above but looking at VSENSE (pink) instead of the aux winding:

And finally, at 200 V input, after successful startup, these are the same waveforms, DRV (green), CS (red), VDS (blue), VSENSE (pink):

How do the same waveforms look on your board?

Bernard

now looking at a new error code having use the force turns in the spread sheet - it was coming up 35:4 instead of 32:4 when i told it a turns ration of 8:1 changing Rb from 41K or 44K to 48K. this got a an error code i had not seen yet: output over voltage... it was going to over 20V and coming back down.  tacked on a 1000uF cap and a 5K resistor before the output inductor...

after putting in a 150V transorb clamp the waveforms are looking good but the reflected voltage is high.  the chip is reporting over voltage now due to the 22V reflected on a 12V output from a 1:1 sec:bias ratio.  might be able to "bring it down" with Rb but i suspect it is the leakage and am not sure how repeatable that would be ... (but i do not really care about absolute accuracy anyhow, anything consistent between 12 and 15V would be fine) 

all have the FET gate in blue... the drain voltage is clamped at 150V but perhalps i should add another 75V transorb:

the current looks like it is ramping up to 1.5A ( 0.5V/0.4 ohm)

the bias winding is "reading" 150V while a meter read 123V and the output as 22V but is only reaching 6 or 8V

Definitely a step in the right direction

105B057.zipit looks like the planar will saturate... the other one that i have handy is 75:12:18 (bias) looks like it might work... really playing games with the numbers though.  That one is only 3KV hipot, 300uH and 15uH leakage with a 5A saturation so the 3.6A that I come up with for max current after diddling looks workable... going to be replacing the resistors to try it so something is at least running

ok the transformer is in... CS=200m, Ra=46.4K, Rb=22.1K ... at nominal the bias is "reading" 150V bulk and 15V or so on the output.  the wave forms are looking much better and i do not seem to be getting any error code accept the VDD under voltage.  

ok still not starting... using a different transformer with lower leakage (that we had in house) and higher output voltage to make the ratios right for the 12V VDD rail.  Using a new scope probe with out the foolish clip leads and have much cleaner wave forms showing the ringing down, but not gone at 1.7uS.

well crap... things are looking better... a lot of the hash was the "probe" leads, but i knew it was:

OK ... running with a Vdd regulator ... must have been rushed: Rb was low .. re-entered the transformer and stuff and increased Rb but the 34.5K suggested caused a fault since the 33.2K I put in did.   running with 30.1K for Rb

you were right about the bias series resister: it was freshly put in but basically open - likely due to my not checking the iron before i started: production likes them set 800 for ROHS ... Always gives me trouble since that tends to boil off both flux and solder before it takes

reports CS pin fault when "starting" into a 1.2A load.  temperature on both the unheatsunk power switch and the transformer are around 38F.  

here are the new bias, drain and spreadsheet files

EDIT: 40V spike on the bias winding looks a bit ugly, guess i might be needing that filter cap on Vsense2727.105B057.zip

Bernard,

I got the new transformer in and running nicely though a bit confusing.

720uH 40:4:4:4 (primary:secondary:bias:secondary) and empirically it seems next to no leakage.  The transformer house measured 750nH leakage on the bias shorting all the other windings for 11% so i put that into the spreadsheet to get resistor values and ended up with only 10V at the output. (and a lot of headaches)

I disconnected the chip from the bias and increased the capacitor to be able to see what was happening safely.   the spreadsheet said to use Ra=19.1K and Rb=38.2K but the data sheet formula said to use 37.7K for 10% leakage.

when i reduced the spreadsheet leakage to 0% it said 26K...  when i put 33.2K in for Rb I get a no load output of 11.4V with a bias voltage of 10.1V and with a 5.2 ohm load i get 11.3V with a bias voltage of 11.7V.  Does this seem typical?

currently there is no snubber other than the 150V clamping diodes and what ringing there is is down almost all the way at 1.5uS.  I notice in the demo there is a piddly little 10pF across the clamping zener, should i bother?

Currently running with no heat sinking at all, but i will add some copper if i get to expand the board a bit.