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The time of VCC Power ON to DEFLDO enable delay for TPS65023

Allen Hsiao
Prodigy 40 points
We would like to know the max. time of VCC Power ON to DEFLDO enable delay.
 
Because we cannot find relative information in spec and needs your help.
  • 0
    TI__Genius 17380 points
    Hi Allen,

    Are you looking for timing related to DEFLDO or LDO_EN?

    DEFLDO should be tied to GND, VCC or a resistor dividor to the output, so timing has no role.

    I will check on typical VCC Power ON to LDO_EN timing based on EVM BOM and setup and assuming LDO_EN is tied to VCC. If this is not what you are concerned with, please help to clarify the exact connections you are interested in and timings. Alternatively, if you would like to run more extensive testing (for example at high or low temperature or with your BOM), the EVM is available here: www.ti.com/.../tps65023evm-205