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LM5069-1 application questions

Don Foong
Expert 4100 points
Other Parts Discussed in Thread: LM5069, LM5060

Hi Team,


We have application questions from our customer hope you can help to advise, thanks.

  1. How will the Power Good Output pin behave if Overcurrent is detected ? For LM5069-1, can we assumed PGD goes low and latched.
  2. If the application do not want to have a Current Limit capability from LM5069, can we just short the Rsense ?

  • 0
    TI__Genius 10370 points

    Hi Don,

    Here are my answers/comments:

    1) The PGD pin will go low after the timer has tripped from an overcurrent event. This is because Vds will become greater than 2.5V at some time after the timer pin reaches its threshold. The GATE is pulled to GND, and the output caps will discharge and create a Vds voltage greater than 2.5V.

    2) The short answer is yes, but understand that the FET won't have protection if the current exceeds the FET's SOA curve. If the customer still doesn't want a current limit, then I suggest to go with the LM5060 instead. The LM5060 doesn't have all of the features of the LM5069, and the current limit function on the LM5060 isn't a true current limit. The device starts the timer once the current reaches the current limit threshold, but it doesn't regulate the current like the LM5069. The LM5060 might be more cost effective since it has less of the bells and whistles than the LM5069.

    I hope this helps Don and thank you for considering our part :-)

    Best Regards,
    Aramis P. Alvarez

  • 0 in reply to Aramis P. Alvarez
    TI__Expert 4100 points
    Hi Alvarez,

    Thanks for the feedback. You have answered the questions. I wanted to select 'Verify Answer' but couldn't find it to select. Thanks.