BQ76940

Hi Bartho,

these settling times are very excessive usual setting times. check the values of the input filter ( Rc, Cc);  the ADC sampling is 12.5mS time slices . If this measurements is being taken BAL/Non BAL, make sure, the measurement is being made after releasing the balancing FET.. cells with longer time constants will have less time to settle and hence more error. cells measured long after the BAL stop should have lower error.

balancing single cell will have MIN disruption.

balancing alternate cells will have MAX disruption.  

Hi Vish Nadarajah,

Thank you for answering my question. I really appreciate it!

The voltage "ripple" seen is due to the specific balancing algorithm used, which behaves as expected.

The problem I have is for example the measurements of cell 2 which stays constant at 3.45 V. There is no measurement noise for over 500 seconds? Possible but highly unlikely. Thereafter the cell voltage reduces linearly from the constant voltage. Please see the attached figure which tries to explain the seen behavior better. Please keep in mind that this behavior is also seen in applications where cell balancing is not active. 

Can you please suggest possible explanations of what could cause this non linear behavior? I have spent quite some time investigating the source of the problem and I could not find a problem within my system. My question ultimately comes down to if this behavior could be attributed to the operation of the BQ chip? Seeing that the measurement error (4mV) is still within the specified accuracy of the BQ's datasheet. 

I would really appreciate some input!

Kind regards,

Bartho

ADC_error.pdf

Hi,

I think a better representation of the behavior I am referring to is shown in the figure below.

Help would be appreciated.

Kind regards,

Bartho

ADC_error_fit.pdf

Hi Bartho,

thanks for documenting the issue and concerns at hand.

reviewing the CELL2-CELL 5 measurement summary,

(1) the artifact of the gradual change is NOT an artifact of the  ADC. On this device we have accelerated temp and aging data (HTOL-dynamic)

data to document the ADC error is very small. 

(2) Seems cells/ systems are  receiving some charging. Where is the pre-charging threshold  set on this cell system?

(3) Lets use ADC-ENA to {off} to check and also check the actual input value.

Hi,

On (1), thanks. Just wanted to make sure. 

(2), this is the battery behavior during a rest period after a pulse discharge. Cells voltages rise gradually as expected.

(3) I will monitor the ADC_ENA during the next test. Will also reset it after each read cycle.

Question, I am not using the  current sensor functionality (coulomb counter) of the BQ chip. Do I need to synchronize the cell voltage measurements with the BQ chip at all?  If yes, how will I achieve that? Currently I am just doing a read once every one second.

Thank you so much for all the help.

Kind regards,

Bartho

Hi, 

My voltage measurements problem still persists. Currently I am still doing an ADC reset after each read cycle. Measurements are read every second, asynchronously. Can this influence the ADC measurements of the chip? If yes please explain how to solve this problem.

Could it possibly be worth it to do measurements synchronously with the BQ76940 chip or isn't it worth the trouble? 

Kind regards,

Bartho

The cell voltage measurement are not taken via the CC path.  The cell voltage is measured via different 14bit ADC, which is mutually exclusive measurement.

 The embedded Scheduler assigns different time slices during cell balancing and non-cell balancing.

Please refer to the Application note, SLUA775- "Embedded Scheduler in cell battery monitor of the bq769x0".

thanks

vish