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TPS63000 - Output behavior of changing from internal clock to external clock

Dice-K
Mastermind 7480 points
Other Parts Discussed in Thread: TPS63000

Hello,
I have a question about TPS63000.

When I operate it with an internal clock and change it to an external clock (= when I put an external clock in SYNC pin), does the output stop?
If the output stops at the time of an external clock change from an internal clock, I use it with an external clock from the beginning.

Regards,
Dice-K

  • 0
    Mastermind 7480 points
    Hello,
    Please help me.

    I want to know whether the change of the clock is possible during IC movement.

    Regards,
    Dice-K
  • 0 in reply to Dice-K
    TI__Expert 8420 points
    You can connect an external clock anytime without VOUT droping. I would be surprised if it does.
  • 0 in reply to Sabrina
    Mastermind 7480 points

    Hello Sabrina,
    Thank you for your reply.

    Let me confirm it.
    Does it mean that VOUT does not drop even if I change TPS63000 to an external clock from the internal clock during TPS63000 movement?

    Best regards,
    Dice-K

  • 0 in reply to Dice-K
    Mastermind 7480 points
    Hello Sabrina.

    SLVS520C describes as follows.

    Page-9 7.4.3 Power-Save Mode and Synchronization
    "Connecting a clock signal at PS/SYNC forces the device to synchronize to the connected clock frequency.
    Synchronization is done by a phase-locked loop (PLL),
    so synchronizing to lower and higher frequencies compared to the internal clock works without any issues.
    The PLL can also tolerate missing clock pulses without the converter malfunctioning."

    From the above description, does it mean that VOUT does not drop even if I change TPS63000 to an external clock from the internal clock during TPS63000 movement?

    Best regards,
    Dice-K
  • 0 in reply to Dice-K
    TI__Expert 8420 points
    I don't expect any issue when the clock is changed from internal to external. I would recommend to order an EVM an double check in your system.
  • 0 in reply to Sabrina
    Mastermind 7480 points

    Hello Sabrina,
    Thank you for your reply.

    For various checking, my customer ordered the EVM.
    But he has two questions first.

    (1)
    From the theory of the IC,
    which of internal clock and external clock is high in the power efficiency?

    (2)
    From the theory of the IC,
    at the time of the change of the internal clock and the external clock, how long time does it take until VOUT is stable?
    For example,
    it takes 1ms for VOUT in ±1% until it is stable.
    (From internal clock to external clock)
    (From external clock to internal clock)

    Or is the VOUT always stable at the time of changing clock, from the following description ?
    "The PLL can also tolerate missing clock pulses without the converter malfunctioning."

    I'm sorry for questions of the repetition.

    Best regards,
    Dice-K

  • 0 in reply to Dice-K
    TI__Expert 8420 points
    I will check with the designer and come back to you
  • 0 in reply to Sabrina
    TI__Expert 8420 points
    The IC is always switching with an internal clock. When external frequency is applied, this internal clock synchronizes itself to the frequency of external clock with the help of PLL. During this process, we expect VOUT to be stable.

    The efficiency would remain similar if the frequency of the external and internal clock are similar. If the frequency of the external clock is higher, then the efficiency would probably be lower.