CEDV low temperature.

Roman Kislicyn

Prodigy 140 points

Other Parts Discussed in Thread: BQ76920, BQ78350

Hello!

I studied CEDV.(bq78350+bq76920)

SLUUBD3B–September 2015–Revised May 2016

9.1.8 End-of-Discharge Thresholds and Capacity Correction

Suppose I set the all parameters of CEDV.
I start the discharge (1 A)
Device discharge at a low temperature(-20 °C ).
Happened a correction capacity (RC).
I stop the discharge(It was not a qualified discharge).

Then I put the device in the room. (At room temperature)
I start the charge

SOC(or RC) reaches up to 100%(or FCC) ?

over 8 years ago

0 Sammi Shang over 8 years ago

TI__Expert 4450 points

Hi Roman,

When discharge at low temperature, the battery will reach EDV quickly than room temperature.The avaliable capacity under low temperature is little than room temperature. So when put the battery in room, SOC and RC will reach up but are not necessarily 100%.

Best regards,

Sammi

0 Roman Kislicyn over 8 years ago in reply to Sammi Shang

Prodigy 140 points

To avoid this need to use chips with "Impedance Track" algorithm?

0 Sammi Shang over 8 years ago in reply to Roman Kislicyn

TI__Expert 4450 points

Both the CEDV and Impedance Track algorithm can smooth the SOC through linear interpolation of the model. So the SOC will not have a heavy drop even take it from low temperature to room. But the usable capacity(FCC) under room temperature is much more than low temperature.

Best regards,
Sammi

Power management

Power management forum

CEDV low temperature.